Lines Matching refs:pll
30 static int dphy_calc_pll_param(struct dphy_pll *pll) in dphy_calc_pll_param() argument
38 pll->potential_fvco = pll->freq / khz; in dphy_calc_pll_param()
39 pll->ref_clk = PHY_REF_CLK / khz; in dphy_calc_pll_param()
42 if (pll->potential_fvco >= VCO_BAND_LOW && in dphy_calc_pll_param()
43 pll->potential_fvco <= VCO_BAND_HIGH) { in dphy_calc_pll_param()
44 pll->fvco = pll->potential_fvco; in dphy_calc_pll_param()
45 pll->out_sel = BIT(i); in dphy_calc_pll_param()
48 pll->potential_fvco <<= 1; in dphy_calc_pll_param()
50 if (pll->fvco == 0) in dphy_calc_pll_param()
53 if (pll->fvco >= VCO_BAND_LOW && pll->fvco <= VCO_BAND_MID) { in dphy_calc_pll_param()
55 pll->vco_band = 0x0; in dphy_calc_pll_param()
57 pll->lpf_sel = 1; in dphy_calc_pll_param()
58 } else if (pll->fvco > VCO_BAND_MID && pll->fvco <= VCO_BAND_HIGH) { in dphy_calc_pll_param()
59 pll->vco_band = 0x1; in dphy_calc_pll_param()
60 pll->lpf_sel = 0; in dphy_calc_pll_param()
65 pll->nint = pll->fvco / pll->ref_clk; in dphy_calc_pll_param()
66 tmp = pll->fvco * factor * mhz; in dphy_calc_pll_param()
67 do_div(tmp, pll->ref_clk); in dphy_calc_pll_param()
68 tmp = tmp - pll->nint * factor * mhz; in dphy_calc_pll_param()
71 pll->kint = (u32)tmp; in dphy_calc_pll_param()
72 pll->refin = 3; /* pre-divider bypass */ in dphy_calc_pll_param()
73 pll->sdm_en = true; /* use fraction N PLL */ in dphy_calc_pll_param()
74 pll->fdk_s = 0x1; /* fraction */ in dphy_calc_pll_param()
75 pll->cp_s = 0x0; in dphy_calc_pll_param()
76 pll->det_delay = 0x1; in dphy_calc_pll_param()
81 static void dphy_set_pll_reg(struct dphy_pll *pll, struct regmap *regmap) in dphy_set_pll_reg() argument
91 reg_val[0] = 1 | (1 << 1) | (pll->lpf_sel << 2); in dphy_set_pll_reg()
92 reg_val[1] = pll->div | (1 << 3) | (pll->cp_s << 5) | (pll->fdk_s << 7); in dphy_set_pll_reg()
93 reg_val[2] = pll->nint; in dphy_set_pll_reg()
94 reg_val[3] = pll->vco_band | (pll->sdm_en << 1) | (pll->refin << 2); in dphy_set_pll_reg()
95 reg_val[4] = pll->kint >> 12; in dphy_set_pll_reg()
96 reg_val[5] = pll->kint >> 4; in dphy_set_pll_reg()
97 reg_val[6] = pll->out_sel | ((pll->kint << 4) & 0xf); in dphy_set_pll_reg()
99 reg_val[8] = pll->det_delay; in dphy_set_pll_reg()
111 struct dphy_pll *pll = &ctx->pll; in dphy_pll_config() local
114 pll->freq = dsi->slave->hs_rate; in dphy_pll_config()
117 ret = dphy_calc_pll_param(pll); in dphy_pll_config()
122 dphy_set_pll_reg(pll, regmap); in dphy_pll_config()
217 struct dphy_pll *pll = &ctx->pll; in dphy_timing_config() local
226 t_ui = 1000 * scale / (pll->freq / 1000); in dphy_timing_config()