Lines Matching refs:tilcdc_clear
134 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); in tilcdc_crtc_load_palette()
136 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA); in tilcdc_crtc_load_palette()
164 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, in tilcdc_crtc_disable_irqs()
167 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, in tilcdc_crtc_disable_irqs()
187 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); in reset()
367 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, in tilcdc_crtc_set_mode()
404 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); in tilcdc_crtc_set_mode()
409 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); in tilcdc_crtc_set_mode()
414 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); in tilcdc_crtc_set_mode()
419 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); in tilcdc_crtc_set_mode()
424 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); in tilcdc_crtc_set_mode()
429 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); in tilcdc_crtc_set_mode()
463 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); in tilcdc_crtc_enable()
505 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); in tilcdc_crtc_off()
722 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, in tilcdc_crtc_disable_vblank()
725 tilcdc_clear(dev, LCDC_INT_ENABLE_SET_REG, in tilcdc_crtc_disable_vblank()
747 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); in tilcdc_crtc_reset()
963 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, in tilcdc_crtc_irq()
977 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, in tilcdc_crtc_irq()
1002 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, in tilcdc_crtc_irq()