Lines Matching refs:pixel_rep
1193 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; in vc4_hdmi_set_timings() local
1219 VC4_SET_FIELD(mode->hdisplay * pixel_rep, in vc4_hdmi_set_timings()
1224 mode->hsync_end) * pixel_rep, in vc4_hdmi_set_timings()
1227 mode->hsync_start) * pixel_rep, in vc4_hdmi_set_timings()
1230 mode->hdisplay) * pixel_rep, in vc4_hdmi_set_timings()
1241 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); in vc4_hdmi_set_timings()
1257 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; in vc5_hdmi_set_timings() local
1263 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), in vc5_hdmi_set_timings()
1285 VC4_SET_FIELD(mode->hdisplay * pixel_rep, in vc5_hdmi_set_timings()
1288 mode->hdisplay) * pixel_rep, in vc5_hdmi_set_timings()
1293 mode->hsync_end) * pixel_rep, in vc5_hdmi_set_timings()
1296 mode->hsync_start) * pixel_rep, in vc5_hdmi_set_timings()
1346 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); in vc5_hdmi_set_timings()