Lines Matching refs:mmio_base

54 	u32 mmio_base;  member
64 		.mmio_base = RENDER_RING_BASE,
72 		.mmio_base = BLT_RING_BASE,
80 		.mmio_base = XEHPC_BCS1_RING_BASE,
88 		.mmio_base = XEHPC_BCS2_RING_BASE,
96 		.mmio_base = XEHPC_BCS3_RING_BASE,
104 		.mmio_base = XEHPC_BCS4_RING_BASE,
112 		.mmio_base = XEHPC_BCS5_RING_BASE,
120 		.mmio_base = XEHPC_BCS6_RING_BASE,
128 		.mmio_base = XEHPC_BCS7_RING_BASE,
136 		.mmio_base = XEHPC_BCS8_RING_BASE,
145 		.mmio_base = BSD_RING_BASE,
153 		.mmio_base = BSD2_RING_BASE,
161 		.mmio_base = BSD3_RING_BASE,
169 		.mmio_base = BSD4_RING_BASE,
177 		.mmio_base = XEHP_BSD5_RING_BASE,
185 		.mmio_base = XEHP_BSD6_RING_BASE,
193 		.mmio_base = XEHP_BSD7_RING_BASE,
201 		.mmio_base = XEHP_BSD8_RING_BASE,
209 		.mmio_base = VEBOX_RING_BASE,
217 		.mmio_base = VEBOX2_RING_BASE,
225 		.mmio_base = XEHP_VEBOX3_RING_BASE,
233 		.mmio_base = XEHP_VEBOX4_RING_BASE,
241 		.mmio_base = COMPUTE0_RING_BASE,
249 		.mmio_base = COMPUTE1_RING_BASE,
257 		.mmio_base = COMPUTE2_RING_BASE,
265 		.mmio_base = COMPUTE3_RING_BASE,
272 		.mmio_base = GSCCS_RING_BASE,
299 	xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base));  in xe_hw_engine_mmio_write32()
302 	reg.addr += hwe->mmio_base;  in xe_hw_engine_mmio_write32()
319 	xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base));  in xe_hw_engine_mmio_read32()
322 	reg.addr += hwe->mmio_base;  in xe_hw_engine_mmio_read32()
512 	hwe->mmio_base = info->mmio_base;  in hw_engine_init_early()
580 		idledly = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));  in adjust_idledly()
581 		maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));  in adjust_idledly()
593 			xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base), idledly);  in adjust_idledly()
908 	snapshot->mmio_base = hwe->mmio_base;  in xe_hw_engine_snapshot_capture()
1032 	return xe_mmio_read64_2x32(&hwe->gt->mmio, RING_TIMESTAMP(hwe->mmio_base));  in xe_hw_engine_read_timestamp()