Lines Matching refs:master_ctl
112 gu_misc_irq_ack(struct xe_device *xe, const u32 master_ctl) in gu_misc_irq_ack() argument
117 if (!(master_ctl & GU_MISC_IRQ)) in gu_misc_irq_ack()
308 u32 master_ctl, unsigned long *intr_dw, in gt_irq_handler() argument
321 if (!(master_ctl & GT_DW_IRQ(bank))) in gt_irq_handler()
371 u32 master_ctl, gu_misc_iir; in xelp_irq_handler() local
378 master_ctl = xelp_intr_disable(xe); in xelp_irq_handler()
379 if (!master_ctl) { in xelp_irq_handler()
384 gt_irq_handler(tile, master_ctl, intr_dw, identity); in xelp_irq_handler()
386 xe_display_irq_handler(xe, master_ctl); in xelp_irq_handler()
388 gu_misc_iir = gu_misc_irq_ack(xe, master_ctl); in xelp_irq_handler()
433 u32 master_tile_ctl, master_ctl = 0, gu_misc_iir = 0; in dg1_irq_handler() local
455 master_ctl = xe_mmio_read32(mmio, GFX_MSTR_IRQ); in dg1_irq_handler()
462 if (master_ctl == REG_GENMASK(31, 0)) { in dg1_irq_handler()
468 xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl); in dg1_irq_handler()
470 gt_irq_handler(tile, master_ctl, intr_dw, identity); in dg1_irq_handler()
479 xe_heci_csc_irq_handler(xe, master_ctl); in dg1_irq_handler()
480 xe_display_irq_handler(xe, master_ctl); in dg1_irq_handler()
481 xe_i2c_irq_handler(xe, master_ctl); in dg1_irq_handler()
482 gu_misc_iir = gu_misc_irq_ack(xe, master_ctl); in dg1_irq_handler()