Lines Matching refs:REG
152 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets() macro
201 REG(0x034),
202 REG(0x030),
203 REG(0x038),
204 REG(0x03c),
205 REG(0x168),
206 REG(0x140),
207 REG(0x110),
208 REG(0x1c0),
209 REG(0x1c4),
210 REG(0x1c8),
211 REG(0x180),
233 REG(0x034),
234 REG(0x030),
235 REG(0x038),
236 REG(0x03c),
237 REG(0x168),
238 REG(0x140),
239 REG(0x110),
240 REG(0x1c0),
241 REG(0x1c4),
242 REG(0x1c8),
243 REG(0x180),
245 REG(0x120),
246 REG(0x124),
267 REG(0x034),
268 REG(0x030),
269 REG(0x038),
270 REG(0x03c),
271 REG(0x168),
272 REG(0x140),
273 REG(0x110),
274 REG(0x1c0),
275 REG(0x1c4),
276 REG(0x1c8),
277 REG(0x180),
293 REG(0x1b0),
299 REG(0x0c8),
309 REG(0x028),
310 REG(0x09c),
311 REG(0x0c0),
312 REG(0x178),
313 REG(0x17c),
315 REG(0x170),
316 REG(0x150),
317 REG(0x154),
318 REG(0x158),
352 REG(0x068),
353 REG(0x084),
363 REG(0x034),
364 REG(0x030),
365 REG(0x038),
366 REG(0x03c),
367 REG(0x168),
368 REG(0x140),
369 REG(0x110),
370 REG(0x1c0),
371 REG(0x1c4),
372 REG(0x1c8),
373 REG(0x180),
389 REG(0x1b0),
395 REG(0x0c8),
404 REG(0x034),
405 REG(0x030),
406 REG(0x038),
407 REG(0x03c),
408 REG(0x168),
409 REG(0x140),
410 REG(0x110),
411 REG(0x1c0),
412 REG(0x1c4),
413 REG(0x1c8),
414 REG(0x180),
416 REG(0x120),
417 REG(0x124),
432 REG(0x1b0),
438 REG(0x0c8),
447 REG(0x034),
448 REG(0x030),
449 REG(0x038),
450 REG(0x03c),
451 REG(0x168),
452 REG(0x140),
453 REG(0x110),
454 REG(0x1c0),
455 REG(0x1c4),
456 REG(0x1c8),
457 REG(0x180),
459 REG(0x120),
460 REG(0x124),
481 REG(0x0c8),
490 REG(0x034), /* [0x04] RING_BUFFER_HEAD */ \
491 REG(0x030), /* [0x06] RING_BUFFER_TAIL */ \
492 REG(0x038), /* [0x08] RING_BUFFER_START */ \
493 REG(0x03c), /* [0x0a] RING_BUFFER_CONTROL */ \
494 REG(0x168), /* [0x0c] BB_ADDR_UDW */ \
495 REG(0x140), /* [0x0e] BB_ADDR */ \
496 REG(0x110), /* [0x10] BB_STATE */ \
497 REG(0x1c0), /* [0x12] BB_PER_CTX_PTR */ \
498 REG(0x1c4), /* [0x14] RCS_INDIRECT_CTX */ \
499 REG(0x1c8), /* [0x16] RCS_INDIRECT_CTX_OFFSET */ \
500 REG(0x180), /* [0x18] CCID */ \
502 REG(0x120), /* [0x1c] PRT_BB_STATE */ \
503 REG(0x124), /* [0x1e] PRT_BB_STATE_UDW */ \
509 REG(0x108), /* [0x26] INDIRECT_RING_STATE */ \
527 REG(0x0c8), /* [0x48] R_PWR_CLK_STATE */
552 REG(0x034), /* [0x02] RING_BUFFER_HEAD */
553 REG(0x030), /* [0x04] RING_BUFFER_TAIL */
554 REG(0x038), /* [0x06] RING_BUFFER_START */
555 REG(0x048), /* [0x08] RING_BUFFER_START_UDW */
556 REG(0x03c), /* [0x0a] RING_BUFFER_CONTROL */
560 REG(0x168), /* [0x12] BB_ADDR_UDW */
561 REG(0x140), /* [0x14] BB_ADDR */
562 REG(0x110), /* [0x16] BB_STATE */
576 #undef REG