Lines Matching refs:BASE
280 const BASE: usize; consts
346 let hwcfg1 = regs::NV_PFALCON_FALCON_HWCFG1::read(bar, E::BASE); in new()
352 let hwcfg2 = regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE); in new()
372 if regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE).mem_scrubbing_done() { in reset_wait_mem_scrubbing()
382 let _ = regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE); in reset_eng()
387 let r = regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE); in reset_eng()
395 regs::NV_PFALCON_FALCON_ENGINE::alter(bar, E::BASE, |v| v.set_reset(true)); in reset_eng()
401 regs::NV_PFALCON_FALCON_ENGINE::alter(bar, E::BASE, |v| v.set_reset(false)); in reset_eng()
416 .write(bar, E::BASE); in reset()
467 .write(bar, E::BASE); in dma_wr()
470 .write(bar, E::BASE); in dma_wr()
481 .write(bar, E::BASE); in dma_wr()
484 .write(bar, E::BASE); in dma_wr()
485 cmd.write(bar, E::BASE); in dma_wr()
491 let r = regs::NV_PFALCON_FALCON_DMATRFCMD::read(bar, E::BASE); in dma_wr()
505 regs::NV_PFALCON_FBIF_CTL::alter(bar, E::BASE, |v| v.set_allow_phys_no_ctx(true)); in dma_load()
506 regs::NV_PFALCON_FALCON_DMACTL::default().write(bar, E::BASE); in dma_load()
507 regs::NV_PFALCON_FBIF_TRANSCFG::alter(bar, E::BASE, |v| { in dma_load()
520 .write(bar, E::BASE); in dma_load()
541 .write(bar, E::BASE); in boot()
547 .write(bar, E::BASE); in boot()
550 match regs::NV_PFALCON_FALCON_CPUCTL::read(bar, E::BASE).alias_en() { in boot()
553 .write(bar, E::BASE), in boot()
556 .write(bar, E::BASE), in boot()
561 let r = regs::NV_PFALCON_FALCON_CPUCTL::read(bar, E::BASE); in boot()
570 regs::NV_PFALCON_FALCON_MAILBOX0::read(bar, E::BASE).value(), in boot()
571 regs::NV_PFALCON_FALCON_MAILBOX1::read(bar, E::BASE).value(), in boot()