Lines Matching refs:bar
343 bar: &Bar0, in new()
346 let hwcfg1 = regs::NV_PFALCON_FALCON_HWCFG1::read(bar, E::BASE); in new()
352 let hwcfg2 = regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE); in new()
369 fn reset_wait_mem_scrubbing(&self, bar: &Bar0) -> Result { in reset_wait_mem_scrubbing()
372 if regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE).mem_scrubbing_done() { in reset_wait_mem_scrubbing()
381 fn reset_eng(&self, bar: &Bar0) -> Result { in reset_eng()
382 let _ = regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE); in reset_eng()
387 let r = regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE); in reset_eng()
395 regs::NV_PFALCON_FALCON_ENGINE::alter(bar, E::BASE, |v| v.set_reset(true)); in reset_eng()
401 regs::NV_PFALCON_FALCON_ENGINE::alter(bar, E::BASE, |v| v.set_reset(false)); in reset_eng()
403 self.reset_wait_mem_scrubbing(bar)?; in reset_eng()
409 pub(crate) fn reset(&self, bar: &Bar0) -> Result { in reset()
410 self.reset_eng(bar)?; in reset()
411 self.hal.select_core(self, bar)?; in reset()
412 self.reset_wait_mem_scrubbing(bar)?; in reset()
415 .set_value(regs::NV_PMC_BOOT_0::read(bar).into()) in reset()
416 .write(bar, E::BASE); in reset()
427 bar: &Bar0, in dma_wr()
467 .write(bar, E::BASE); in dma_wr()
470 .write(bar, E::BASE); in dma_wr()
481 .write(bar, E::BASE); in dma_wr()
484 .write(bar, E::BASE); in dma_wr()
485 cmd.write(bar, E::BASE); in dma_wr()
491 let r = regs::NV_PFALCON_FALCON_DMATRFCMD::read(bar, E::BASE); in dma_wr()
504 pub(crate) fn dma_load<F: FalconFirmware<Target = E>>(&self, bar: &Bar0, fw: &F) -> Result { in dma_load()
505 regs::NV_PFALCON_FBIF_CTL::alter(bar, E::BASE, |v| v.set_allow_phys_no_ctx(true)); in dma_load()
506 regs::NV_PFALCON_FALCON_DMACTL::default().write(bar, E::BASE); in dma_load()
507 regs::NV_PFALCON_FBIF_TRANSCFG::alter(bar, E::BASE, |v| { in dma_load()
512 self.dma_wr(bar, fw, FalconMem::Imem, fw.imem_load_params(), true)?; in dma_load()
513 self.dma_wr(bar, fw, FalconMem::Dmem, fw.dmem_load_params(), true)?; in dma_load()
515 self.hal.program_brom(self, bar, &fw.brom_params())?; in dma_load()
520 .write(bar, E::BASE); in dma_load()
534 bar: &Bar0, in boot()
541 .write(bar, E::BASE); in boot()
547 .write(bar, E::BASE); in boot()
550 match regs::NV_PFALCON_FALCON_CPUCTL::read(bar, E::BASE).alias_en() { in boot()
553 .write(bar, E::BASE), in boot()
556 .write(bar, E::BASE), in boot()
561 let r = regs::NV_PFALCON_FALCON_CPUCTL::read(bar, E::BASE); in boot()
570 regs::NV_PFALCON_FALCON_MAILBOX0::read(bar, E::BASE).value(), in boot()
571 regs::NV_PFALCON_FALCON_MAILBOX1::read(bar, E::BASE).value(), in boot()
581 bar: &Bar0, in signature_reg_fuse_version()
586 .signature_reg_fuse_version(self, bar, engine_id_mask, ucode_id) in signature_reg_fuse_version()