Lines Matching refs:reg_base
60 value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); in iris_vpu3x_hw_power_collapsed()
76 value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); in iris_vpu3_power_off_hardware()
78 writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); in iris_vpu3_power_off_hardware()
81 ret = readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN + 4 * i, in iris_vpu3_power_off_hardware()
87 writel(VIDEO_NOC_RESET_REQ, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); in iris_vpu3_power_off_hardware()
89 ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, in iris_vpu3_power_off_hardware()
94 writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); in iris_vpu3_power_off_hardware()
96 ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, in iris_vpu3_power_off_hardware()
102 core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); in iris_vpu3_power_off_hardware()
103 writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); in iris_vpu3_power_off_hardware()
104 writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); in iris_vpu3_power_off_hardware()
120 value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); in iris_vpu33_power_off_hardware()
122 writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); in iris_vpu33_power_off_hardware()
125 ret = readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN + 4 * i, in iris_vpu33_power_off_hardware()
131 ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, in iris_vpu33_power_off_hardware()
137 writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); in iris_vpu33_power_off_hardware()
140 core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); in iris_vpu33_power_off_hardware()
141 writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); in iris_vpu33_power_off_hardware()
142 writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); in iris_vpu33_power_off_hardware()
155 writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH); in iris_vpu33_power_off_controller()
157 writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL); in iris_vpu33_power_off_controller()
159 ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS, in iris_vpu33_power_off_controller()
164 writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL); in iris_vpu33_power_off_controller()
166 ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS, in iris_vpu33_power_off_controller()
172 core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); in iris_vpu33_power_off_controller()
173 writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); in iris_vpu33_power_off_controller()
174 writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); in iris_vpu33_power_off_controller()
175 writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); in iris_vpu33_power_off_controller()
180 val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); in iris_vpu33_power_off_controller()
182 writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); in iris_vpu33_power_off_controller()
185 val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); in iris_vpu33_power_off_controller()
187 writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); in iris_vpu33_power_off_controller()
190 ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_SPARE, in iris_vpu33_power_off_controller()
196 val = readl(core->reg_base + AON_WRAPPER_SPARE); in iris_vpu33_power_off_controller()
198 writel(val, core->reg_base + AON_WRAPPER_SPARE); in iris_vpu33_power_off_controller()
203 val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); in iris_vpu33_power_off_controller()
205 writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); in iris_vpu33_power_off_controller()
212 writel(0, core->reg_base + AON_WRAPPER_SPARE); in iris_vpu33_power_off_controller()
215 val = readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); in iris_vpu33_power_off_controller()
217 writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); in iris_vpu33_power_off_controller()