Lines Matching refs:read

493 	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))  in flexcan_low_power_enter_ack()
496 	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))  in flexcan_low_power_enter_ack()
507 	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))  in flexcan_low_power_exit_ack()
510 	if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)  in flexcan_low_power_exit_ack()
521 	reg_mcr = priv->read(&regs->mcr);  in flexcan_enable_wakeup_irq()
554 	reg_mcr = priv->read(&regs->mcr);  in flexcan_enter_stop_mode()
598 	reg_mcr = priv->read(&regs->mcr);  in flexcan_exit_stop_mode()
671 	reg = priv->read(&regs->mcr);  in flexcan_chip_enable()
683 	reg = priv->read(&regs->mcr);  in flexcan_chip_disable()
702 	reg = priv->read(&regs->mcr);  in flexcan_chip_freeze()
706 	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))  in flexcan_chip_freeze()
709 	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))  in flexcan_chip_freeze()
721 	reg = priv->read(&regs->mcr);  in flexcan_chip_unfreeze()
725 	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))  in flexcan_chip_unfreeze()
728 	if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)  in flexcan_chip_unfreeze()
740 	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))  in flexcan_chip_softreset()
743 	if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)  in flexcan_chip_softreset()
754 	u32 reg = priv->read(&regs->ecr);  in __flexcan_get_berr_counter()
841 	timestamp = priv->read(&regs->timer) << 16;  in flexcan_irq_bus_err()
924 	timestamp = priv->read(&regs->timer) << 16;  in flexcan_irq_state()
945 		reg = (u64)priv->read(addr - 4) << 32;  in flexcan_read64_mask()
947 		reg |= priv->read(addr);  in flexcan_read64_mask()
993 			reg_ctrl = priv->read(&mb->can_ctrl);  in flexcan_mailbox_read()
1008 		reg_iflag1 = priv->read(&regs->iflag1);  in flexcan_mailbox_read()
1012 		reg_ctrl = priv->read(&mb->can_ctrl);  in flexcan_mailbox_read()
1032 	reg_id = priv->read(&mb->can_id);  in flexcan_mailbox_read()
1054 		__be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));  in flexcan_mailbox_read()
1068 	priv->read(&regs->timer);  in flexcan_mailbox_read()
1099 		reg_iflag1 = priv->read(&regs->iflag1);  in flexcan_irq()
1119 		u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);  in flexcan_irq()
1134 	reg_esr = priv->read(&regs->esr);  in flexcan_irq()
1204 	reg = priv->read(&regs->ctrl);  in flexcan_set_bittiming_ctrl()
1222 		   priv->read(&regs->mcr), priv->read(&regs->ctrl));  in flexcan_set_bittiming_ctrl()
1275 		reg_fdcbt = priv->read(&regs->fdcbt);  in flexcan_set_bittiming_cbt()
1292 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_set_bittiming_cbt()
1302 	reg_fdctrl = priv->read(&regs->fdctrl);  in flexcan_set_bittiming_cbt()
1326 		   priv->read(&regs->mcr), priv->read(&regs->ctrl),  in flexcan_set_bittiming_cbt()
1327 		   priv->read(&regs->ctrl2), priv->read(&regs->fdctrl),  in flexcan_set_bittiming_cbt()
1328 		   priv->read(&regs->cbt), priv->read(&regs->fdcbt));  in flexcan_set_bittiming_cbt()
1337 	reg = priv->read(&regs->ctrl);  in flexcan_set_bittiming()
1371 	reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_ram_init()
1495 	reg_mcr = priv->read(&regs->mcr);  in flexcan_chip_start()
1548 	reg_ctrl = priv->read(&regs->ctrl);  in flexcan_chip_start()
1571 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_chip_start()
1579 		reg_fdctrl = priv->read(&regs->fdctrl);  in flexcan_chip_start()
1652 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_chip_start()
1657 		reg_mecr = priv->read(&regs->mecr);  in flexcan_chip_start()
1685 		   priv->read(&regs->mcr), priv->read(&regs->ctrl));  in flexcan_chip_start()
1888 	reg = priv->read(&regs->ctrl);  in register_flexcandev()
1905 	reg = priv->read(&regs->mcr);  in register_flexcandev()
1914 	reg = priv->read(&regs->mcr);  in register_flexcandev()
2193 		priv->read = flexcan_read_be;  in flexcan_probe()
2196 		priv->read = flexcan_read_le;  in flexcan_probe()