Lines Matching refs:cdev
330 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg) in m_can_read() argument
332 return cdev->ops->read_reg(cdev, reg); in m_can_read()
335 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg, in m_can_write() argument
338 cdev->ops->write_reg(cdev, reg, val); in m_can_write()
342 m_can_fifo_read(struct m_can_classdev *cdev, in m_can_fifo_read() argument
345 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE + in m_can_fifo_read()
351 return cdev->ops->read_fifo(cdev, addr_offset, val, val_count); in m_can_fifo_read()
355 m_can_fifo_write(struct m_can_classdev *cdev, in m_can_fifo_write() argument
358 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE + in m_can_fifo_write()
364 return cdev->ops->write_fifo(cdev, addr_offset, val, val_count); in m_can_fifo_write()
367 static inline int m_can_fifo_write_no_off(struct m_can_classdev *cdev, in m_can_fifo_write_no_off() argument
370 return cdev->ops->write_fifo(cdev, fpi, &val, 1); in m_can_fifo_write_no_off()
374 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset, u32 *val) in m_can_txe_fifo_read() argument
376 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE + in m_can_txe_fifo_read()
379 return cdev->ops->read_fifo(cdev, addr_offset, val, 1); in m_can_txe_fifo_read()
382 static int m_can_cccr_update_bits(struct m_can_classdev *cdev, u32 mask, u32 val) in m_can_cccr_update_bits() argument
384 u32 val_before = m_can_read(cdev, M_CAN_CCCR); in m_can_cccr_update_bits()
389 dev_err(cdev->dev, in m_can_cccr_update_bits()
408 m_can_write(cdev, M_CAN_CCCR, val_after); in m_can_cccr_update_bits()
410 val_read = m_can_read(cdev, M_CAN_CCCR) & ~(CCCR_CSR | CCCR_CSA); in m_can_cccr_update_bits()
421 static int m_can_config_enable(struct m_can_classdev *cdev) in m_can_config_enable() argument
429 err = m_can_cccr_update_bits(cdev, CCCR_CCE, CCCR_CCE); in m_can_config_enable()
431 netdev_err(cdev->net, "failed to enable configuration mode\n"); in m_can_config_enable()
436 static int m_can_config_disable(struct m_can_classdev *cdev) in m_can_config_disable() argument
443 err = m_can_cccr_update_bits(cdev, CCCR_CCE, 0); in m_can_config_disable()
445 netdev_err(cdev->net, "failed to disable configuration registers\n"); in m_can_config_disable()
450 static void m_can_interrupt_enable(struct m_can_classdev *cdev, u32 interrupts) in m_can_interrupt_enable() argument
452 if (cdev->active_interrupts == interrupts) in m_can_interrupt_enable()
454 cdev->ops->write_reg(cdev, M_CAN_IE, interrupts); in m_can_interrupt_enable()
455 cdev->active_interrupts = interrupts; in m_can_interrupt_enable()
458 static void m_can_coalescing_disable(struct m_can_classdev *cdev) in m_can_coalescing_disable() argument
460 u32 new_interrupts = cdev->active_interrupts | IR_RF0N | IR_TEFN; in m_can_coalescing_disable()
462 if (!cdev->net->irq) in m_can_coalescing_disable()
465 hrtimer_cancel(&cdev->hrtimer); in m_can_coalescing_disable()
466 m_can_interrupt_enable(cdev, new_interrupts); in m_can_coalescing_disable()
469 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev) in m_can_enable_all_interrupts() argument
471 if (!cdev->net->irq) { in m_can_enable_all_interrupts()
472 dev_dbg(cdev->dev, "Start hrtimer\n"); in m_can_enable_all_interrupts()
473 hrtimer_start(&cdev->hrtimer, in m_can_enable_all_interrupts()
479 m_can_write(cdev, M_CAN_ILE, ILE_EINT0); in m_can_enable_all_interrupts()
482 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev) in m_can_disable_all_interrupts() argument
484 m_can_coalescing_disable(cdev); in m_can_disable_all_interrupts()
485 m_can_write(cdev, M_CAN_ILE, 0x0); in m_can_disable_all_interrupts()
487 if (!cdev->net->irq) { in m_can_disable_all_interrupts()
488 dev_dbg(cdev->dev, "Stop hrtimer\n"); in m_can_disable_all_interrupts()
489 hrtimer_try_to_cancel(&cdev->hrtimer); in m_can_disable_all_interrupts()
496 static u32 m_can_get_timestamp(struct m_can_classdev *cdev) in m_can_get_timestamp() argument
501 tscv = m_can_read(cdev, M_CAN_TSCV); in m_can_get_timestamp()
509 struct m_can_classdev *cdev = netdev_priv(net); in m_can_clean() local
512 if (cdev->tx_ops) { in m_can_clean()
513 for (int i = 0; i != cdev->tx_fifo_size; ++i) { in m_can_clean()
514 if (!cdev->tx_ops[i].skb) in m_can_clean()
518 cdev->tx_ops[i].skb = NULL; in m_can_clean()
522 for (int i = 0; i != cdev->can.echo_skb_max; ++i) in m_can_clean()
523 can_free_echo_skb(cdev->net, i, NULL); in m_can_clean()
525 netdev_reset_queue(cdev->net); in m_can_clean()
527 spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags); in m_can_clean()
528 cdev->tx_fifo_in_flight = 0; in m_can_clean()
529 spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags); in m_can_clean()
537 static void m_can_receive_skb(struct m_can_classdev *cdev, in m_can_receive_skb() argument
541 if (cdev->is_peripheral) { in m_can_receive_skb()
542 struct net_device_stats *stats = &cdev->net->stats; in m_can_receive_skb()
545 err = can_rx_offload_queue_timestamp(&cdev->offload, skb, in m_can_receive_skb()
557 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_read_fifo() local
564 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID, &fifo_header, 2); in m_can_read_fifo()
598 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DATA, in m_can_read_fifo()
609 m_can_receive_skb(cdev, skb, timestamp); in m_can_read_fifo()
622 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_do_rx_poll() local
631 rxfs = m_can_read(cdev, M_CAN_RXF0S); in m_can_do_rx_poll()
648 fgi = (++fgi >= cdev->mcfg[MRAM_RXF0].num ? 0 : fgi); in m_can_do_rx_poll()
652 m_can_write(cdev, M_CAN_RXF0A, ack_fgi); in m_can_do_rx_poll()
662 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_lost_msg() local
680 if (cdev->is_peripheral) in m_can_handle_lost_msg()
681 timestamp = m_can_get_timestamp(cdev); in m_can_handle_lost_msg()
683 m_can_receive_skb(cdev, skb, timestamp); in m_can_handle_lost_msg()
691 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_lec_err() local
697 cdev->can.can_stats.bus_error++; in m_can_handle_lec_err()
752 if (cdev->is_peripheral) in m_can_handle_lec_err()
753 timestamp = m_can_get_timestamp(cdev); in m_can_handle_lec_err()
755 m_can_receive_skb(cdev, skb, timestamp); in m_can_handle_lec_err()
763 struct m_can_classdev *cdev = netdev_priv(dev); in __m_can_get_berr_counter() local
766 ecr = m_can_read(cdev, M_CAN_ECR); in __m_can_get_berr_counter()
773 static int m_can_clk_start(struct m_can_classdev *cdev) in m_can_clk_start() argument
775 if (cdev->pm_clock_support == 0) in m_can_clk_start()
778 return pm_runtime_resume_and_get(cdev->dev); in m_can_clk_start()
781 static void m_can_clk_stop(struct m_can_classdev *cdev) in m_can_clk_stop() argument
783 if (cdev->pm_clock_support) in m_can_clk_stop()
784 pm_runtime_put_sync(cdev->dev); in m_can_clk_stop()
790 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_get_berr_counter() local
793 err = m_can_clk_start(cdev); in m_can_get_berr_counter()
799 m_can_clk_stop(cdev); in m_can_get_berr_counter()
807 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_state_change() local
817 cdev->can.can_stats.error_warning++; in m_can_handle_state_change()
818 cdev->can.state = CAN_STATE_ERROR_WARNING; in m_can_handle_state_change()
822 cdev->can.can_stats.error_passive++; in m_can_handle_state_change()
823 cdev->can.state = CAN_STATE_ERROR_PASSIVE; in m_can_handle_state_change()
827 cdev->can.state = CAN_STATE_BUS_OFF; in m_can_handle_state_change()
828 m_can_disable_all_interrupts(cdev); in m_can_handle_state_change()
829 cdev->can.can_stats.bus_off++; in m_can_handle_state_change()
856 ecr = m_can_read(cdev, M_CAN_ECR); in m_can_handle_state_change()
872 if (cdev->is_peripheral) in m_can_handle_state_change()
873 timestamp = m_can_get_timestamp(cdev); in m_can_handle_state_change()
875 m_can_receive_skb(cdev, skb, timestamp); in m_can_handle_state_change()
882 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_state_errors() local
885 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) { in m_can_handle_state_errors()
891 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) { in m_can_handle_state_errors()
897 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) { in m_can_handle_state_errors()
933 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_protocol_error() local
945 if (cdev->version >= 31 && (irqstatus & IR_PEA)) { in m_can_handle_protocol_error()
947 cdev->can.can_stats.arbitration_lost++; in m_can_handle_protocol_error()
959 if (cdev->is_peripheral) in m_can_handle_protocol_error()
960 timestamp = m_can_get_timestamp(cdev); in m_can_handle_protocol_error()
962 m_can_receive_skb(cdev, skb, timestamp); in m_can_handle_protocol_error()
970 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_bus_errors() local
977 if (cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) { in m_can_handle_bus_errors()
993 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && in m_can_handle_bus_errors()
1005 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_rx_handler() local
1022 if (cdev->version <= 31 && irqstatus & IR_MRAF && in m_can_rx_handler()
1023 m_can_read(cdev, M_CAN_ECR) & ECR_RP) { in m_can_rx_handler()
1028 m_can_write(cdev, M_CAN_IR, IR_MRAF); in m_can_rx_handler()
1035 m_can_read(cdev, M_CAN_PSR)); in m_can_rx_handler()
1039 m_can_read(cdev, M_CAN_PSR)); in m_can_rx_handler()
1055 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_poll() local
1059 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR); in m_can_poll()
1068 m_can_enable_all_interrupts(cdev); in m_can_poll()
1078 static unsigned int m_can_tx_update_stats(struct m_can_classdev *cdev, in m_can_tx_update_stats() argument
1081 struct net_device *dev = cdev->net; in m_can_tx_update_stats()
1085 if (cdev->is_peripheral) in m_can_tx_update_stats()
1087 can_rx_offload_get_echo_skb_queue_timestamp(&cdev->offload, in m_can_tx_update_stats()
1099 static void m_can_finish_tx(struct m_can_classdev *cdev, int transmitted, in m_can_finish_tx() argument
1104 netdev_completed_queue(cdev->net, transmitted, transmitted_frame_len); in m_can_finish_tx()
1106 spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags); in m_can_finish_tx()
1107 if (cdev->tx_fifo_in_flight >= cdev->tx_fifo_size && transmitted > 0) in m_can_finish_tx()
1108 netif_wake_queue(cdev->net); in m_can_finish_tx()
1109 cdev->tx_fifo_in_flight -= transmitted; in m_can_finish_tx()
1110 spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags); in m_can_finish_tx()
1113 static netdev_tx_t m_can_start_tx(struct m_can_classdev *cdev) in m_can_start_tx() argument
1118 spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags); in m_can_start_tx()
1119 tx_fifo_in_flight = cdev->tx_fifo_in_flight + 1; in m_can_start_tx()
1120 if (tx_fifo_in_flight >= cdev->tx_fifo_size) { in m_can_start_tx()
1121 netif_stop_queue(cdev->net); in m_can_start_tx()
1122 if (tx_fifo_in_flight > cdev->tx_fifo_size) { in m_can_start_tx()
1123 netdev_err_once(cdev->net, "hard_xmit called while TX FIFO full\n"); in m_can_start_tx()
1124 spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags); in m_can_start_tx()
1128 cdev->tx_fifo_in_flight = tx_fifo_in_flight; in m_can_start_tx()
1129 spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags); in m_can_start_tx()
1146 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_echo_tx_event() local
1149 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS); in m_can_echo_tx_event()
1160 err = m_can_txe_fifo_read(cdev, fgi, 4, &txe); in m_can_echo_tx_event()
1170 fgi = (++fgi >= cdev->mcfg[MRAM_TXE].num ? 0 : fgi); in m_can_echo_tx_event()
1173 processed_frame_len += m_can_tx_update_stats(cdev, msg_mark, in m_can_echo_tx_event()
1180 m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK, in m_can_echo_tx_event()
1183 m_can_finish_tx(cdev, processed, processed_frame_len); in m_can_echo_tx_event()
1188 static void m_can_coalescing_update(struct m_can_classdev *cdev, u32 ir) in m_can_coalescing_update() argument
1190 u32 new_interrupts = cdev->active_interrupts; in m_can_coalescing_update()
1194 if (!cdev->net->irq) in m_can_coalescing_update()
1197 if (cdev->rx_coalesce_usecs_irq > 0 && (ir & (IR_RF0N | IR_RF0W))) { in m_can_coalescing_update()
1201 if (cdev->tx_coalesce_usecs_irq > 0 && (ir & (IR_TEFN | IR_TEFW))) { in m_can_coalescing_update()
1205 if (!enable_rx_timer && !hrtimer_active(&cdev->hrtimer)) in m_can_coalescing_update()
1207 if (!enable_tx_timer && !hrtimer_active(&cdev->hrtimer)) in m_can_coalescing_update()
1210 m_can_interrupt_enable(cdev, new_interrupts); in m_can_coalescing_update()
1212 hrtimer_start(&cdev->hrtimer, cdev->irq_timer_wait, in m_can_coalescing_update()
1220 static int m_can_interrupt_handler(struct m_can_classdev *cdev) in m_can_interrupt_handler() argument
1222 struct net_device *dev = cdev->net; in m_can_interrupt_handler()
1226 if (pm_runtime_suspended(cdev->dev)) in m_can_interrupt_handler()
1235 while ((ir_read = m_can_read(cdev, M_CAN_IR)) != 0) { in m_can_interrupt_handler()
1239 m_can_write(cdev, M_CAN_IR, ir); in m_can_interrupt_handler()
1241 if (!cdev->irq_edge_triggered) in m_can_interrupt_handler()
1245 m_can_coalescing_update(cdev, ir); in m_can_interrupt_handler()
1249 if (cdev->ops->clear_interrupts) in m_can_interrupt_handler()
1250 cdev->ops->clear_interrupts(cdev); in m_can_interrupt_handler()
1258 cdev->irqstatus = ir; in m_can_interrupt_handler()
1259 if (!cdev->is_peripheral) { in m_can_interrupt_handler()
1260 m_can_disable_all_interrupts(cdev); in m_can_interrupt_handler()
1261 napi_schedule(&cdev->napi); in m_can_interrupt_handler()
1269 if (cdev->version == 30) { in m_can_interrupt_handler()
1275 if (cdev->is_peripheral) in m_can_interrupt_handler()
1276 timestamp = m_can_get_timestamp(cdev); in m_can_interrupt_handler()
1277 frame_len = m_can_tx_update_stats(cdev, 0, timestamp); in m_can_interrupt_handler()
1278 m_can_finish_tx(cdev, 1, frame_len); in m_can_interrupt_handler()
1289 if (cdev->is_peripheral) in m_can_interrupt_handler()
1290 can_rx_offload_threaded_irq_finish(&cdev->offload); in m_can_interrupt_handler()
1298 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_isr() local
1301 ret = m_can_interrupt_handler(cdev); in m_can_isr()
1303 m_can_disable_all_interrupts(cdev); in m_can_isr()
1312 struct m_can_classdev *cdev = container_of(timer, struct m_can_classdev, hrtimer); in m_can_coalescing_timer() local
1314 if (cdev->can.state == CAN_STATE_BUS_OFF || in m_can_coalescing_timer()
1315 cdev->can.state == CAN_STATE_STOPPED) in m_can_coalescing_timer()
1318 irq_wake_thread(cdev->net->irq, cdev->net); in m_can_coalescing_timer()
1373 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_set_bittiming() local
1374 const struct can_bittiming *bt = &cdev->can.bittiming; in m_can_set_bittiming()
1375 const struct can_bittiming *dbt = &cdev->can.fd.data_bittiming; in m_can_set_bittiming()
1387 m_can_write(cdev, M_CAN_NBTP, reg_btp); in m_can_set_bittiming()
1389 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { in m_can_set_bittiming()
1411 tdco = (cdev->can.clock.freq / 1000) * in m_can_set_bittiming()
1422 m_can_write(cdev, M_CAN_TDCR, in m_can_set_bittiming()
1431 m_can_write(cdev, M_CAN_DBTP, reg_btp); in m_can_set_bittiming()
1449 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_chip_config() local
1454 err = m_can_init_ram(cdev); in m_can_chip_config()
1456 dev_err(cdev->dev, "Message RAM configuration failed\n"); in m_can_chip_config()
1465 err = m_can_config_enable(cdev); in m_can_chip_config()
1470 m_can_write(cdev, M_CAN_RXESC, in m_can_chip_config()
1476 m_can_write(cdev, M_CAN_GFC, 0x0); in m_can_chip_config()
1478 if (cdev->version == 30) { in m_can_chip_config()
1480 m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) | in m_can_chip_config()
1481 cdev->mcfg[MRAM_TXB].off); in m_can_chip_config()
1484 m_can_write(cdev, M_CAN_TXBC, in m_can_chip_config()
1486 cdev->mcfg[MRAM_TXB].num) | in m_can_chip_config()
1487 cdev->mcfg[MRAM_TXB].off); in m_can_chip_config()
1491 m_can_write(cdev, M_CAN_TXESC, in m_can_chip_config()
1495 if (cdev->version == 30) { in m_can_chip_config()
1496 m_can_write(cdev, M_CAN_TXEFC, in m_can_chip_config()
1498 cdev->mcfg[MRAM_TXE].off); in m_can_chip_config()
1501 m_can_write(cdev, M_CAN_TXEFC, in m_can_chip_config()
1503 cdev->tx_max_coalesced_frames_irq) | in m_can_chip_config()
1505 cdev->mcfg[MRAM_TXE].num) | in m_can_chip_config()
1506 cdev->mcfg[MRAM_TXE].off); in m_can_chip_config()
1510 m_can_write(cdev, M_CAN_RXF0C, in m_can_chip_config()
1511 FIELD_PREP(RXFC_FWM_MASK, cdev->rx_max_coalesced_frames_irq) | in m_can_chip_config()
1512 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF0].num) | in m_can_chip_config()
1513 cdev->mcfg[MRAM_RXF0].off); in m_can_chip_config()
1515 m_can_write(cdev, M_CAN_RXF1C, in m_can_chip_config()
1516 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF1].num) | in m_can_chip_config()
1517 cdev->mcfg[MRAM_RXF1].off); in m_can_chip_config()
1519 cccr = m_can_read(cdev, M_CAN_CCCR); in m_can_chip_config()
1520 test = m_can_read(cdev, M_CAN_TEST); in m_can_chip_config()
1522 if (cdev->version == 30) { in m_can_chip_config()
1529 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) in m_can_chip_config()
1538 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) in m_can_chip_config()
1541 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) in m_can_chip_config()
1546 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { in m_can_chip_config()
1552 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) in m_can_chip_config()
1556 if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) in m_can_chip_config()
1560 m_can_write(cdev, M_CAN_CCCR, cccr); in m_can_chip_config()
1561 m_can_write(cdev, M_CAN_TEST, test); in m_can_chip_config()
1564 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { in m_can_chip_config()
1565 if (cdev->version == 30) in m_can_chip_config()
1570 cdev->active_interrupts = 0; in m_can_chip_config()
1571 m_can_interrupt_enable(cdev, interrupts); in m_can_chip_config()
1574 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0); in m_can_chip_config()
1582 m_can_write(cdev, M_CAN_TSCC, in m_can_chip_config()
1586 err = m_can_config_disable(cdev); in m_can_chip_config()
1590 if (cdev->ops->init) in m_can_chip_config()
1591 cdev->ops->init(cdev); in m_can_chip_config()
1598 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_start() local
1606 netdev_queue_set_dql_min_limit(netdev_get_tx_queue(cdev->net, 0), in m_can_start()
1607 cdev->tx_max_coalesced_frames); in m_can_start()
1609 cdev->can.state = CAN_STATE_ERROR_ACTIVE; in m_can_start()
1611 m_can_enable_all_interrupts(cdev); in m_can_start()
1613 if (cdev->version > 30) in m_can_start()
1614 cdev->tx_fifo_putidx = FIELD_GET(TXFQS_TFQPI_MASK, in m_can_start()
1615 m_can_read(cdev, M_CAN_TXFQS)); in m_can_start()
1617 ret = m_can_cccr_update_bits(cdev, CCCR_INIT, 0); in m_can_start()
1644 static int m_can_check_core_release(struct m_can_classdev *cdev) in m_can_check_core_release() argument
1654 crel_reg = m_can_read(cdev, M_CAN_CREL); in m_can_check_core_release()
1672 static int m_can_niso_supported(struct m_can_classdev *cdev) in m_can_niso_supported() argument
1676 ret = m_can_config_enable(cdev); in m_can_niso_supported()
1681 niso = m_can_cccr_update_bits(cdev, CCCR_NISO, CCCR_NISO); in m_can_niso_supported()
1684 ret = m_can_cccr_update_bits(cdev, CCCR_NISO, 0); in m_can_niso_supported()
1686 dev_err(cdev->dev, "failed to revert the NON-ISO bit in CCCR\n"); in m_can_niso_supported()
1690 ret = m_can_config_disable(cdev); in m_can_niso_supported()
1697 static int m_can_dev_setup(struct m_can_classdev *cdev) in m_can_dev_setup() argument
1699 struct net_device *dev = cdev->net; in m_can_dev_setup()
1702 m_can_version = m_can_check_core_release(cdev); in m_can_dev_setup()
1705 dev_err(cdev->dev, "Unsupported version number: %2d", in m_can_dev_setup()
1714 err = m_can_cccr_update_bits(cdev, CCCR_INIT, CCCR_INIT); in m_can_dev_setup()
1718 if (!cdev->is_peripheral) in m_can_dev_setup()
1719 netif_napi_add(dev, &cdev->napi, m_can_poll); in m_can_dev_setup()
1722 cdev->version = m_can_version; in m_can_dev_setup()
1723 cdev->can.do_set_mode = m_can_set_mode; in m_can_dev_setup()
1724 cdev->can.do_get_berr_counter = m_can_get_berr_counter; in m_can_dev_setup()
1727 cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | in m_can_dev_setup()
1734 switch (cdev->version) { in m_can_dev_setup()
1740 cdev->can.bittiming_const = &m_can_bittiming_const_30X; in m_can_dev_setup()
1741 cdev->can.fd.data_bittiming_const = &m_can_data_bittiming_const_30X; in m_can_dev_setup()
1748 cdev->can.bittiming_const = &m_can_bittiming_const_31X; in m_can_dev_setup()
1749 cdev->can.fd.data_bittiming_const = &m_can_data_bittiming_const_31X; in m_can_dev_setup()
1754 cdev->can.bittiming_const = &m_can_bittiming_const_31X; in m_can_dev_setup()
1755 cdev->can.fd.data_bittiming_const = &m_can_data_bittiming_const_31X; in m_can_dev_setup()
1757 niso = m_can_niso_supported(cdev); in m_can_dev_setup()
1761 cdev->can.ctrlmode_supported |= CAN_CTRLMODE_FD_NON_ISO; in m_can_dev_setup()
1764 dev_err(cdev->dev, "Unsupported version number: %2d", in m_can_dev_setup()
1765 cdev->version); in m_can_dev_setup()
1774 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_stop() local
1778 m_can_disable_all_interrupts(cdev); in m_can_stop()
1781 ret = m_can_cccr_update_bits(cdev, CCCR_INIT, CCCR_INIT); in m_can_stop()
1787 cdev->can.state = CAN_STATE_STOPPED; in m_can_stop()
1789 if (cdev->ops->deinit) { in m_can_stop()
1790 ret = cdev->ops->deinit(cdev); in m_can_stop()
1799 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_close() local
1809 if (cdev->is_peripheral) { in m_can_close()
1810 destroy_workqueue(cdev->tx_wq); in m_can_close()
1811 cdev->tx_wq = NULL; in m_can_close()
1812 can_rx_offload_disable(&cdev->offload); in m_can_close()
1814 napi_disable(&cdev->napi); in m_can_close()
1819 m_can_clk_stop(cdev); in m_can_close()
1820 phy_power_off(cdev->transceiver); in m_can_close()
1825 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev, in m_can_tx_handler() argument
1831 struct net_device *dev = cdev->net; in m_can_tx_handler()
1849 if (cdev->version == 30) { in m_can_tx_handler()
1855 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, &fifo_element, 2); in m_can_tx_handler()
1859 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_DATA, in m_can_tx_handler()
1864 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { in m_can_tx_handler()
1865 cccr = m_can_read(cdev, M_CAN_CCCR); in m_can_tx_handler()
1877 m_can_write(cdev, M_CAN_CCCR, cccr); in m_can_tx_handler()
1879 m_can_write(cdev, M_CAN_TXBTIE, 0x1); in m_can_tx_handler()
1883 m_can_write(cdev, M_CAN_TXBAR, 0x1); in m_can_tx_handler()
1889 putidx = cdev->tx_fifo_putidx; in m_can_tx_handler()
1911 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, in m_can_tx_handler()
1921 if (cdev->is_peripheral) { in m_can_tx_handler()
1923 cdev->tx_peripheral_submit |= BIT(putidx); in m_can_tx_handler()
1926 m_can_write(cdev, M_CAN_TXBAR, BIT(putidx)); in m_can_tx_handler()
1928 cdev->tx_fifo_putidx = (++cdev->tx_fifo_putidx >= cdev->can.echo_skb_max ? in m_can_tx_handler()
1929 0 : cdev->tx_fifo_putidx); in m_can_tx_handler()
1936 m_can_disable_all_interrupts(cdev); in m_can_tx_handler()
1940 static void m_can_tx_submit(struct m_can_classdev *cdev) in m_can_tx_submit() argument
1942 if (cdev->version == 30) in m_can_tx_submit()
1944 if (!cdev->is_peripheral) in m_can_tx_submit()
1947 m_can_write(cdev, M_CAN_TXBAR, cdev->tx_peripheral_submit); in m_can_tx_submit()
1948 cdev->tx_peripheral_submit = 0; in m_can_tx_submit()
1954 struct m_can_classdev *cdev = op->cdev; in m_can_tx_work_queue() local
1958 m_can_tx_handler(cdev, skb); in m_can_tx_work_queue()
1960 m_can_tx_submit(cdev); in m_can_tx_work_queue()
1963 static void m_can_tx_queue_skb(struct m_can_classdev *cdev, struct sk_buff *skb, in m_can_tx_queue_skb() argument
1966 cdev->tx_ops[cdev->next_tx_op].skb = skb; in m_can_tx_queue_skb()
1967 cdev->tx_ops[cdev->next_tx_op].submit = submit; in m_can_tx_queue_skb()
1968 queue_work(cdev->tx_wq, &cdev->tx_ops[cdev->next_tx_op].work); in m_can_tx_queue_skb()
1970 ++cdev->next_tx_op; in m_can_tx_queue_skb()
1971 if (cdev->next_tx_op >= cdev->tx_fifo_size) in m_can_tx_queue_skb()
1972 cdev->next_tx_op = 0; in m_can_tx_queue_skb()
1975 static netdev_tx_t m_can_start_peripheral_xmit(struct m_can_classdev *cdev, in m_can_start_peripheral_xmit() argument
1980 ++cdev->nr_txs_without_submit; in m_can_start_peripheral_xmit()
1981 if (cdev->nr_txs_without_submit >= cdev->tx_max_coalesced_frames || in m_can_start_peripheral_xmit()
1983 cdev->nr_txs_without_submit = 0; in m_can_start_peripheral_xmit()
1988 m_can_tx_queue_skb(cdev, skb, submit); in m_can_start_peripheral_xmit()
1996 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_start_xmit() local
2005 if (cdev->can.state == CAN_STATE_BUS_OFF) { in m_can_start_xmit()
2006 m_can_clean(cdev->net); in m_can_start_xmit()
2010 ret = m_can_start_tx(cdev); in m_can_start_xmit()
2016 if (cdev->is_peripheral) in m_can_start_xmit()
2017 ret = m_can_start_peripheral_xmit(cdev, skb); in m_can_start_xmit()
2019 ret = m_can_tx_handler(cdev, skb); in m_can_start_xmit()
2029 struct m_can_classdev *cdev = container_of(timer, struct in hrtimer_callback() local
2033 if (cdev->can.state == CAN_STATE_BUS_OFF || in hrtimer_callback()
2034 cdev->can.state == CAN_STATE_STOPPED) in hrtimer_callback()
2037 ret = m_can_interrupt_handler(cdev); in hrtimer_callback()
2040 if (ret < 0 || napi_is_scheduled(&cdev->napi)) in hrtimer_callback()
2050 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_open() local
2053 err = phy_power_on(cdev->transceiver); in m_can_open()
2057 err = m_can_clk_start(cdev); in m_can_open()
2068 if (cdev->is_peripheral) in m_can_open()
2069 can_rx_offload_enable(&cdev->offload); in m_can_open()
2071 napi_enable(&cdev->napi); in m_can_open()
2074 if (cdev->is_peripheral) { in m_can_open()
2075 cdev->tx_wq = alloc_ordered_workqueue("mcan_wq", in m_can_open()
2077 if (!cdev->tx_wq) { in m_can_open()
2082 for (int i = 0; i != cdev->tx_fifo_size; ++i) { in m_can_open()
2083 cdev->tx_ops[i].cdev = cdev; in m_can_open()
2084 INIT_WORK(&cdev->tx_ops[i].work, m_can_tx_work_queue); in m_can_open()
2110 if (cdev->is_peripheral || dev->irq) in m_can_open()
2113 if (cdev->is_peripheral) in m_can_open()
2114 destroy_workqueue(cdev->tx_wq); in m_can_open()
2116 if (cdev->is_peripheral) in m_can_open()
2117 can_rx_offload_disable(&cdev->offload); in m_can_open()
2119 napi_disable(&cdev->napi); in m_can_open()
2122 m_can_clk_stop(cdev); in m_can_open()
2124 phy_power_off(cdev->transceiver); in m_can_open()
2140 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_get_coalesce() local
2142 ec->rx_max_coalesced_frames_irq = cdev->rx_max_coalesced_frames_irq; in m_can_get_coalesce()
2143 ec->rx_coalesce_usecs_irq = cdev->rx_coalesce_usecs_irq; in m_can_get_coalesce()
2144 ec->tx_max_coalesced_frames = cdev->tx_max_coalesced_frames; in m_can_get_coalesce()
2145 ec->tx_max_coalesced_frames_irq = cdev->tx_max_coalesced_frames_irq; in m_can_get_coalesce()
2146 ec->tx_coalesce_usecs_irq = cdev->tx_coalesce_usecs_irq; in m_can_get_coalesce()
2156 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_set_coalesce() local
2158 if (cdev->can.state != CAN_STATE_STOPPED) { in m_can_set_coalesce()
2163 if (ec->rx_max_coalesced_frames_irq > cdev->mcfg[MRAM_RXF0].num) { in m_can_set_coalesce()
2166 cdev->mcfg[MRAM_RXF0].num); in m_can_set_coalesce()
2173 if (ec->tx_max_coalesced_frames_irq > cdev->mcfg[MRAM_TXE].num) { in m_can_set_coalesce()
2176 cdev->mcfg[MRAM_TXE].num); in m_can_set_coalesce()
2179 if (ec->tx_max_coalesced_frames_irq > cdev->mcfg[MRAM_TXB].num) { in m_can_set_coalesce()
2182 cdev->mcfg[MRAM_TXB].num); in m_can_set_coalesce()
2189 if (ec->tx_max_coalesced_frames > cdev->mcfg[MRAM_TXE].num) { in m_can_set_coalesce()
2192 cdev->mcfg[MRAM_TXE].num); in m_can_set_coalesce()
2195 if (ec->tx_max_coalesced_frames > cdev->mcfg[MRAM_TXB].num) { in m_can_set_coalesce()
2198 cdev->mcfg[MRAM_TXB].num); in m_can_set_coalesce()
2209 cdev->rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in m_can_set_coalesce()
2210 cdev->rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in m_can_set_coalesce()
2211 cdev->tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in m_can_set_coalesce()
2212 cdev->tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in m_can_set_coalesce()
2213 cdev->tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in m_can_set_coalesce()
2215 if (cdev->rx_coalesce_usecs_irq) in m_can_set_coalesce()
2216 cdev->irq_timer_wait = in m_can_set_coalesce()
2217 ns_to_ktime(cdev->rx_coalesce_usecs_irq * NSEC_PER_USEC); in m_can_set_coalesce()
2219 cdev->irq_timer_wait = in m_can_set_coalesce()
2220 ns_to_ktime(cdev->tx_coalesce_usecs_irq * NSEC_PER_USEC); in m_can_set_coalesce()
2240 static int register_m_can_dev(struct m_can_classdev *cdev) in register_m_can_dev() argument
2242 struct net_device *dev = cdev->net; in register_m_can_dev()
2246 if (dev->irq && cdev->is_peripheral) in register_m_can_dev()
2254 int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size) in m_can_check_mram_cfg() argument
2258 total_size = cdev->mcfg[MRAM_TXB].off - cdev->mcfg[MRAM_SIDF].off + in m_can_check_mram_cfg()
2259 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; in m_can_check_mram_cfg()
2261 dev_err(cdev->dev, "Total size of mram config(%u) exceeds mram(%u)\n", in m_can_check_mram_cfg()
2270 static void m_can_of_parse_mram(struct m_can_classdev *cdev, in m_can_of_parse_mram() argument
2273 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0]; in m_can_of_parse_mram()
2274 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1]; in m_can_of_parse_mram()
2275 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off + in m_can_of_parse_mram()
2276 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; in m_can_of_parse_mram()
2277 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2]; in m_can_of_parse_mram()
2278 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off + in m_can_of_parse_mram()
2279 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; in m_can_of_parse_mram()
2280 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] & in m_can_of_parse_mram()
2282 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off + in m_can_of_parse_mram()
2283 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; in m_can_of_parse_mram()
2284 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] & in m_can_of_parse_mram()
2286 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off + in m_can_of_parse_mram()
2287 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; in m_can_of_parse_mram()
2288 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5]; in m_can_of_parse_mram()
2289 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off + in m_can_of_parse_mram()
2290 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; in m_can_of_parse_mram()
2291 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6]; in m_can_of_parse_mram()
2292 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off + in m_can_of_parse_mram()
2293 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; in m_can_of_parse_mram()
2294 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] & in m_can_of_parse_mram()
2297 dev_dbg(cdev->dev, in m_can_of_parse_mram()
2299 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num, in m_can_of_parse_mram()
2300 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num, in m_can_of_parse_mram()
2301 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num, in m_can_of_parse_mram()
2302 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num, in m_can_of_parse_mram()
2303 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num, in m_can_of_parse_mram()
2304 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num, in m_can_of_parse_mram()
2305 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num); in m_can_of_parse_mram()
2308 int m_can_init_ram(struct m_can_classdev *cdev) in m_can_init_ram() argument
2316 start = cdev->mcfg[MRAM_SIDF].off; in m_can_init_ram()
2317 end = cdev->mcfg[MRAM_TXB].off + in m_can_init_ram()
2318 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; in m_can_init_ram()
2321 err = m_can_fifo_write_no_off(cdev, i, 0x0); in m_can_init_ram()
2330 int m_can_class_get_clocks(struct m_can_classdev *cdev) in m_can_class_get_clocks() argument
2334 cdev->hclk = devm_clk_get(cdev->dev, "hclk"); in m_can_class_get_clocks()
2335 cdev->cclk = devm_clk_get(cdev->dev, "cclk"); in m_can_class_get_clocks()
2337 if (IS_ERR(cdev->hclk) || IS_ERR(cdev->cclk)) { in m_can_class_get_clocks()
2338 dev_err(cdev->dev, "no clock found\n"); in m_can_class_get_clocks()
2394 int m_can_class_register(struct m_can_classdev *cdev) in m_can_class_register() argument
2398 cdev->tx_fifo_size = max(1, min(cdev->mcfg[MRAM_TXB].num, in m_can_class_register()
2399 cdev->mcfg[MRAM_TXE].num)); in m_can_class_register()
2400 if (cdev->is_peripheral) { in m_can_class_register()
2401 cdev->tx_ops = in m_can_class_register()
2402 devm_kzalloc(cdev->dev, in m_can_class_register()
2403 cdev->tx_fifo_size * sizeof(*cdev->tx_ops), in m_can_class_register()
2405 if (!cdev->tx_ops) { in m_can_class_register()
2406 dev_err(cdev->dev, "Failed to allocate tx_ops for workqueue\n"); in m_can_class_register()
2411 ret = m_can_clk_start(cdev); in m_can_class_register()
2415 if (cdev->is_peripheral) { in m_can_class_register()
2416 ret = can_rx_offload_add_manual(cdev->net, &cdev->offload, in m_can_class_register()
2422 if (!cdev->net->irq) { in m_can_class_register()
2423 dev_dbg(cdev->dev, "Polling enabled, initialize hrtimer"); in m_can_class_register()
2424 hrtimer_setup(&cdev->hrtimer, &hrtimer_callback, CLOCK_MONOTONIC, in m_can_class_register()
2427 hrtimer_setup(&cdev->hrtimer, m_can_coalescing_timer, CLOCK_MONOTONIC, in m_can_class_register()
2431 ret = m_can_dev_setup(cdev); in m_can_class_register()
2435 ret = register_m_can_dev(cdev); in m_can_class_register()
2437 dev_err(cdev->dev, "registering %s failed (err=%d)\n", in m_can_class_register()
2438 cdev->net->name, ret); in m_can_class_register()
2442 of_can_transceiver(cdev->net); in m_can_class_register()
2444 dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n", in m_can_class_register()
2445 KBUILD_MODNAME, cdev->net->irq, cdev->version); in m_can_class_register()
2450 m_can_clk_stop(cdev); in m_can_class_register()
2455 if (cdev->is_peripheral) in m_can_class_register()
2456 can_rx_offload_del(&cdev->offload); in m_can_class_register()
2458 m_can_clk_stop(cdev); in m_can_class_register()
2464 void m_can_class_unregister(struct m_can_classdev *cdev) in m_can_class_unregister() argument
2466 unregister_candev(cdev->net); in m_can_class_unregister()
2467 if (cdev->is_peripheral) in m_can_class_unregister()
2468 can_rx_offload_del(&cdev->offload); in m_can_class_unregister()
2474 struct m_can_classdev *cdev = dev_get_drvdata(dev); in m_can_class_suspend() local
2475 struct net_device *ndev = cdev->net; in m_can_class_suspend()
2486 if (cdev->pm_wake_source) { in m_can_class_suspend()
2487 hrtimer_cancel(&cdev->hrtimer); in m_can_class_suspend()
2488 m_can_write(cdev, M_CAN_IE, IR_RF0N); in m_can_class_suspend()
2490 if (cdev->ops->deinit) in m_can_class_suspend()
2491 ret = cdev->ops->deinit(cdev); in m_can_class_suspend()
2496 m_can_clk_stop(cdev); in m_can_class_suspend()
2501 cdev->can.state = CAN_STATE_SLEEPING; in m_can_class_suspend()
2509 struct m_can_classdev *cdev = dev_get_drvdata(dev); in m_can_class_resume() local
2510 struct net_device *ndev = cdev->net; in m_can_class_resume()
2515 cdev->can.state = CAN_STATE_ERROR_ACTIVE; in m_can_class_resume()
2518 ret = m_can_clk_start(cdev); in m_can_class_resume()
2522 if (cdev->pm_wake_source) { in m_can_class_resume()
2529 cdev->active_interrupts |= IR_RF0N | IR_TEFN; in m_can_class_resume()
2531 if (cdev->ops->init) in m_can_class_resume()
2532 ret = cdev->ops->init(cdev); in m_can_class_resume()
2534 m_can_write(cdev, M_CAN_IE, cdev->active_interrupts); in m_can_class_resume()
2538 m_can_clk_stop(cdev); in m_can_class_resume()