Lines Matching refs:ioaddr
17 int dwmac_dma_reset(void __iomem *ioaddr) in dwmac_dma_reset() argument
19 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()
23 writel(value, ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()
25 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, in dwmac_dma_reset()
31 void dwmac_enable_dma_transmission(void __iomem *ioaddr, u32 chan) in dwmac_enable_dma_transmission() argument
33 writel(1, ioaddr + DMA_CHAN_XMT_POLL_DEMAND(chan)); in dwmac_enable_dma_transmission()
36 void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, in dwmac_enable_dma_irq() argument
39 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac_enable_dma_irq()
46 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac_enable_dma_irq()
49 void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, in dwmac_disable_dma_irq() argument
52 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac_disable_dma_irq()
59 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac_disable_dma_irq()
62 void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, in dwmac_dma_start_tx() argument
65 u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); in dwmac_dma_start_tx()
67 writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); in dwmac_dma_start_tx()
70 void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) in dwmac_dma_stop_tx() argument
72 u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); in dwmac_dma_stop_tx()
74 writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); in dwmac_dma_stop_tx()
77 void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, in dwmac_dma_start_rx() argument
80 u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); in dwmac_dma_start_rx()
82 writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); in dwmac_dma_start_rx()
85 void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) in dwmac_dma_stop_rx() argument
87 u32 value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); in dwmac_dma_stop_rx()
89 writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); in dwmac_dma_stop_rx()
162 int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, in dwmac_dma_interrupt() argument
168 u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan)); in dwmac_dma_interrupt()
214 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_dma_interrupt()
238 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); in dwmac_dma_interrupt()
243 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) in dwmac_dma_flush_tx_fifo() argument
245 u32 csr6 = readl(ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo()
246 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo()
248 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); in dwmac_dma_flush_tx_fifo()
251 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], in stmmac_set_mac_addr() argument
261 writel(data | GMAC_HI_REG_AE, ioaddr + high); in stmmac_set_mac_addr()
263 writel(data, ioaddr + low); in stmmac_set_mac_addr()
268 void stmmac_set_mac(void __iomem *ioaddr, bool enable) in stmmac_set_mac() argument
272 old_val = readl(ioaddr + MAC_CTRL_REG); in stmmac_set_mac()
281 writel(value, ioaddr + MAC_CTRL_REG); in stmmac_set_mac()
284 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, in stmmac_get_mac_addr() argument
290 hi_addr = readl(ioaddr + high); in stmmac_get_mac_addr()
291 lo_addr = readl(ioaddr + low); in stmmac_get_mac_addr()