Lines Matching refs:val
28 static int phy_ts_base_write(struct phy_device *phydev, u32 regnum, u16 val) in phy_ts_base_write() argument
34 val); in phy_ts_base_write()
68 u32 val, cnt = 0; in vsc85xx_ts_read_csr() local
93 val = phy_ts_base_read(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL); in vsc85xx_ts_read_csr()
94 } while (!(val & BIU_ADDR_EXE) && cnt++ < BIU_ADDR_CNT_MAX); in vsc85xx_ts_read_csr()
96 val = phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_MSB); in vsc85xx_ts_read_csr()
97 val <<= 16; in vsc85xx_ts_read_csr()
98 val |= phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_LSB); in vsc85xx_ts_read_csr()
104 return val; in vsc85xx_ts_read_csr()
108 u16 addr, u32 val) in vsc85xx_ts_write_csr() argument
112 u32 reg, bypass, cnt = 0, lower = val & 0xffff, upper = val >> 16; in vsc85xx_ts_write_csr()
191 u32 val = 0; in vsc85xx_ts_fsb_init() local
194 val = (val << 6) | sig_sel[pos]; in vsc85xx_ts_fsb_init()
197 val); in vsc85xx_ts_fsb_init()
248 u32 val, ingr_latency, egr_latency; in vsc85xx_ts_set_latencies() local
278 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_set_latencies()
280 val |= PHY_PTP_INGR_TSP_CTRL_LOAD_DELAYS; in vsc85xx_ts_set_latencies()
282 val); in vsc85xx_ts_set_latencies()
287 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL); in vsc85xx_ts_set_latencies()
288 val |= PHY_PTP_EGR_TSP_CTRL_LOAD_DELAYS; in vsc85xx_ts_set_latencies()
289 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val); in vsc85xx_ts_set_latencies()
347 u32 val; in vsc85xx_ts_eth_cmp1_sig() local
349 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT); in vsc85xx_ts_eth_cmp1_sig()
350 val &= ~ANA_ETH1_NTX_PROT_SIG_OFF_MASK; in vsc85xx_ts_eth_cmp1_sig()
351 val |= ANA_ETH1_NTX_PROT_SIG_OFF(0); in vsc85xx_ts_eth_cmp1_sig()
352 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT, val); in vsc85xx_ts_eth_cmp1_sig()
354 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG); in vsc85xx_ts_eth_cmp1_sig()
355 val &= ~ANA_FSB_ADDR_FROM_BLOCK_SEL_MASK; in vsc85xx_ts_eth_cmp1_sig()
356 val |= ANA_FSB_ADDR_FROM_ETH1; in vsc85xx_ts_eth_cmp1_sig()
357 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG, val); in vsc85xx_ts_eth_cmp1_sig()
514 u32 val; in vsc85xx_ptp_cmp_init() local
522 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_ptp_cmp_init()
524 val &= ~PTP_FLOW_DOMAIN_RANGE_ENA; in vsc85xx_ptp_cmp_init()
526 MSCC_ANA_PTP_FLOW_DOMAIN_RANGE(i), val); in vsc85xx_ptp_cmp_init()
544 u32 val; in vsc85xx_eth_cmp1_init() local
562 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_eth_cmp1_init()
564 val &= ~ANA_ETH1_FLOW_MATCH_VLAN_TAG_MASK; in vsc85xx_eth_cmp1_init()
565 val |= ANA_ETH1_FLOW_MATCH_VLAN_VERIFY; in vsc85xx_eth_cmp1_init()
567 val); in vsc85xx_eth_cmp1_init()
576 u32 val; in vsc85xx_ip_cmp1_init() local
587 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0)); in vsc85xx_ip_cmp1_init()
588 val &= ~IP1_FLOW_ENA_CHANNEL_MASK_MASK; in vsc85xx_ip_cmp1_init()
589 val |= base ? IP1_FLOW_VALID_CH0 : IP1_FLOW_VALID_CH1; in vsc85xx_ip_cmp1_init()
590 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val); in vsc85xx_ip_cmp1_init()
617 u32 val; in vsc85xx_adjfine() local
626 val = PTP_AUTO_ADJ_NS_ROLLOVER(adj); in vsc85xx_adjfine()
627 val |= scaled_ppm > 0 ? PTP_AUTO_ADJ_ADD_1NS : PTP_AUTO_ADJ_SUB_1NS; in vsc85xx_adjfine()
633 val); in vsc85xx_adjfine()
636 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in vsc85xx_adjfine()
637 val |= PTP_LTC_CTRL_AUTO_ADJ_UPDATE; in vsc85xx_adjfine()
638 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in vsc85xx_adjfine()
651 u32 val; in __vsc85xx_gettime() local
655 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in __vsc85xx_gettime()
656 val |= PTP_LTC_CTRL_SAVE_ENA; in __vsc85xx_gettime()
657 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_gettime()
665 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc85xx_gettime()
668 ts->tv_sec = ((time64_t)val) << 32; in __vsc85xx_gettime()
670 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc85xx_gettime()
672 ts->tv_sec += val; in __vsc85xx_gettime()
703 u32 val; in __vsc85xx_settime() local
714 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in __vsc85xx_settime()
715 val |= PTP_LTC_CTRL_LOAD_ENA; in __vsc85xx_settime()
716 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_settime()
724 val &= ~PTP_LTC_CTRL_LOAD_ENA; in __vsc85xx_settime()
725 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_settime()
752 u32 val; in vsc85xx_adjtime() local
773 val = PTP_LTC_OFFSET_VAL(abs(delta)) | PTP_LTC_OFFSET_ADJ; in vsc85xx_adjtime()
775 val |= PTP_LTC_OFFSET_ADD; in vsc85xx_adjtime()
776 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_OFFSET, val); in vsc85xx_adjtime()
786 u32 val; in vsc85xx_eth1_next_comp() local
788 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT); in vsc85xx_eth1_next_comp()
789 val &= ~ANA_ETH1_NTX_PROT_COMPARATOR_MASK; in vsc85xx_eth1_next_comp()
790 val |= next_comp; in vsc85xx_eth1_next_comp()
791 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, val); in vsc85xx_eth1_next_comp()
793 val = ANA_ETH1_NXT_PROT_ETYPE_MATCH(etype) | in vsc85xx_eth1_next_comp()
796 MSCC_PHY_ANA_ETH1_NXT_PROT_ETYPE_MATCH, val); in vsc85xx_eth1_next_comp()
813 u32 val; in vsc85xx_ts_ptp_action_flow() local
816 val = PTP_FLOW_PTP_0_FIELD_PTP_FRAME | PTP_FLOW_PTP_0_FIELD_RSVRD_CHECK; in vsc85xx_ts_ptp_action_flow()
818 MSCC_ANA_PTP_FLOW_PTP_0_FIELD(flow), val); in vsc85xx_ts_ptp_action_flow()
820 val = PTP_FLOW_PTP_ACTION_CORR_OFFSET(8) | in vsc85xx_ts_ptp_action_flow()
825 val |= PTP_FLOW_PTP_ACTION_SAVE_LOCAL_TIME; in vsc85xx_ts_ptp_action_flow()
827 val |= PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_UPDATE | in vsc85xx_ts_ptp_action_flow()
830 val); in vsc85xx_ts_ptp_action_flow()
834 val = PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(34) | in vsc85xx_ts_ptp_action_flow()
838 val = PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(0) | in vsc85xx_ts_ptp_action_flow()
842 val = PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(16) | in vsc85xx_ts_ptp_action_flow()
845 MSCC_ANA_PTP_FLOW_PTP_ACTION2(flow), val); in vsc85xx_ts_ptp_action_flow()
857 u32 val; in vsc85xx_ptp_conf() local
872 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_ptp_conf()
874 val &= ~PTP_FLOW_ENA; in vsc85xx_ptp_conf()
876 val |= PTP_FLOW_ENA; in vsc85xx_ptp_conf()
878 val); in vsc85xx_ptp_conf()
888 u32 val = ANA_ETH1_FLOW_ADDR_MATCH2_DEST; in vsc85xx_eth1_conf() local
894 val |= ANA_ETH1_FLOW_ADDR_MATCH2_FULL_ADDR | in vsc85xx_eth1_conf()
897 MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), val); in vsc85xx_eth1_conf()
902 val |= ANA_ETH1_FLOW_ADDR_MATCH2_ANY_MULTICAST; in vsc85xx_eth1_conf()
903 val |= ANA_ETH1_FLOW_ADDR_MATCH2_ANY_UNICAST; in vsc85xx_eth1_conf()
905 MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), val); in vsc85xx_eth1_conf()
910 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0)); in vsc85xx_eth1_conf()
911 val &= ~ETH1_FLOW_ENA; in vsc85xx_eth1_conf()
913 val |= ETH1_FLOW_ENA; in vsc85xx_eth1_conf()
914 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), val); in vsc85xx_eth1_conf()
922 u32 val; in vsc85xx_ip1_conf() local
929 val = ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MASK(0xff) | in vsc85xx_ip1_conf()
933 val); in vsc85xx_ip1_conf()
939 val = vsc85xx_ts_read_csr(phydev, blk, in vsc85xx_ip1_conf()
941 val &= ~(IP1_NXT_PROT_UDP_CHKSUM_OFF_MASK | in vsc85xx_ip1_conf()
943 val |= IP1_NXT_PROT_UDP_CHKSUM_WIDTH(2); in vsc85xx_ip1_conf()
945 val &= ~(IP1_NXT_PROT_UDP_CHKSUM_UPDATE | in vsc85xx_ip1_conf()
950 val |= IP1_NXT_PROT_UDP_CHKSUM_OFF(26); in vsc85xx_ip1_conf()
952 val |= IP1_NXT_PROT_UDP_CHKSUM_CLEAR; in vsc85xx_ip1_conf()
954 val); in vsc85xx_ip1_conf()
956 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0)); in vsc85xx_ip1_conf()
957 val &= ~(IP1_FLOW_MATCH_ADDR_MASK | IP1_FLOW_ENA); in vsc85xx_ip1_conf()
958 val |= IP1_FLOW_MATCH_DEST_SRC_ADDR; in vsc85xx_ip1_conf()
960 val |= IP1_FLOW_ENA; in vsc85xx_ip1_conf()
961 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val); in vsc85xx_ip1_conf()
971 u32 val; in vsc85xx_ts_engine_init() local
975 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_engine_init()
978 val &= ~(PTP_ANALYZER_MODE_EGR_ENA(BIT(eng_id)) | in vsc85xx_ts_engine_init()
981 val); in vsc85xx_ts_engine_init()
1016 val &= ~PTP_ANALYZER_MODE_EGR_ENA(BIT(eng_id)); in vsc85xx_ts_engine_init()
1018 val |= PTP_ANALYZER_MODE_EGR_ENA(BIT(eng_id)); in vsc85xx_ts_engine_init()
1020 val &= ~PTP_ANALYZER_MODE_INGR_ENA(BIT(eng_id)); in vsc85xx_ts_engine_init()
1022 val |= PTP_ANALYZER_MODE_INGR_ENA(BIT(eng_id)); in vsc85xx_ts_engine_init()
1025 val); in vsc85xx_ts_engine_init()
1041 u32 val; in vsc85xx_ts_reset_fifo() local
1043 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_ts_reset_fifo()
1045 val |= PTP_EGR_TS_FIFO_RESET; in vsc85xx_ts_reset_fifo()
1047 val); in vsc85xx_ts_reset_fifo()
1049 val &= ~PTP_EGR_TS_FIFO_RESET; in vsc85xx_ts_reset_fifo()
1051 val); in vsc85xx_ts_reset_fifo()
1062 u32 val; in vsc85xx_hwtstamp() local
1099 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1101 val &= ~PTP_INGR_PREDICTOR_EN; in vsc85xx_hwtstamp()
1103 val); in vsc85xx_hwtstamp()
1104 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1106 val &= ~PTP_EGR_PREDICTOR_EN; in vsc85xx_hwtstamp()
1108 val); in vsc85xx_hwtstamp()
1111 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL); in vsc85xx_hwtstamp()
1112 val &= ~(PTP_IFACE_CTRL_EGR_BYPASS | PTP_IFACE_CTRL_INGR_BYPASS); in vsc85xx_hwtstamp()
1114 val |= PTP_IFACE_CTRL_EGR_BYPASS; in vsc85xx_hwtstamp()
1116 val |= PTP_IFACE_CTRL_INGR_BYPASS; in vsc85xx_hwtstamp()
1117 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in vsc85xx_hwtstamp()
1125 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1127 val |= PTP_INGR_PREDICTOR_EN; in vsc85xx_hwtstamp()
1129 val); in vsc85xx_hwtstamp()
1130 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in vsc85xx_hwtstamp()
1132 val |= PTP_EGR_PREDICTOR_EN; in vsc85xx_hwtstamp()
1134 val); in vsc85xx_hwtstamp()
1280 u32 val; in __vsc8584_init_ptp() local
1301 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1303 val &= ~PTP_INGR_PREDICTOR_EN; in __vsc8584_init_ptp()
1305 val); in __vsc8584_init_ptp()
1306 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1308 val &= ~PTP_EGR_PREDICTOR_EN; in __vsc8584_init_ptp()
1310 val); in __vsc8584_init_ptp()
1313 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL); in __vsc8584_init_ptp()
1314 val &= ~PTP_LTC_CTRL_CLK_SEL_MASK; in __vsc8584_init_ptp()
1315 val |= PTP_LTC_CTRL_CLK_SEL_INTERNAL_250; in __vsc8584_init_ptp()
1316 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc8584_init_ptp()
1318 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE); in __vsc8584_init_ptp()
1319 val &= ~PTP_LTC_SEQUENCE_A_MASK; in __vsc8584_init_ptp()
1320 val |= PTP_LTC_SEQUENCE_A(ltc_seq_a[PHC_CLK_250MHZ]); in __vsc8584_init_ptp()
1321 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE, val); in __vsc8584_init_ptp()
1323 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ); in __vsc8584_init_ptp()
1324 val &= ~(PTP_LTC_SEQ_ERR_MASK | PTP_LTC_SEQ_ADD_SUB); in __vsc8584_init_ptp()
1326 val |= PTP_LTC_SEQ_ADD_SUB; in __vsc8584_init_ptp()
1327 val |= PTP_LTC_SEQ_ERR(ltc_seq_e[PHC_CLK_250MHZ]); in __vsc8584_init_ptp()
1328 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ, val); in __vsc8584_init_ptp()
1344 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1346 val &= ~(PTP_ACCUR_PPS_OUT_BYPASS | PTP_ACCUR_PPS_IN_BYPASS | in __vsc8584_init_ptp()
1349 val |= PTP_ACCUR_PPS_OUT_CALIB_ERR | PTP_ACCUR_PPS_OUT_CALIB_DONE | in __vsc8584_init_ptp()
1355 val); in __vsc8584_init_ptp()
1357 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1359 val |= PTP_ACCUR_CALIB_TRIGG; in __vsc8584_init_ptp()
1361 val); in __vsc8584_init_ptp()
1363 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1365 val &= ~PTP_ACCUR_CALIB_TRIGG; in __vsc8584_init_ptp()
1366 val |= PTP_ACCUR_PPS_OUT_CALIB_ERR | PTP_ACCUR_PPS_OUT_CALIB_DONE | in __vsc8584_init_ptp()
1372 val); in __vsc8584_init_ptp()
1374 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1376 val |= PTP_ACCUR_CALIB_TRIGG; in __vsc8584_init_ptp()
1378 val); in __vsc8584_init_ptp()
1380 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1382 val &= ~PTP_ACCUR_CALIB_TRIGG; in __vsc8584_init_ptp()
1384 val); in __vsc8584_init_ptp()
1387 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1389 val &= ~PTP_TSTAMP_FIFO_SI_EN; in __vsc8584_init_ptp()
1391 val); in __vsc8584_init_ptp()
1393 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1395 val &= ~PTP_INGR_REWRITER_REDUCE_PREAMBLE; in __vsc8584_init_ptp()
1397 val); in __vsc8584_init_ptp()
1398 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1400 val &= ~PTP_EGR_REWRITER_REDUCE_PREAMBLE; in __vsc8584_init_ptp()
1402 val); in __vsc8584_init_ptp()
1405 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1407 val |= PTP_INGR_REWRITER_FLAG_BIT_OFF(7) | PTP_INGR_REWRITER_FLAG_VAL; in __vsc8584_init_ptp()
1409 val); in __vsc8584_init_ptp()
1410 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1412 val |= PTP_EGR_REWRITER_FLAG_BIT_OFF(7); in __vsc8584_init_ptp()
1413 val &= ~PTP_EGR_REWRITER_FLAG_VAL; in __vsc8584_init_ptp()
1415 val); in __vsc8584_init_ptp()
1420 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1422 val |= PHY_PTP_INGR_TSP_CTRL_FRACT_NS; in __vsc8584_init_ptp()
1424 val); in __vsc8584_init_ptp()
1426 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL); in __vsc8584_init_ptp()
1427 val |= PHY_PTP_EGR_TSP_CTRL_FRACT_NS; in __vsc8584_init_ptp()
1428 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val); in __vsc8584_init_ptp()
1430 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1432 val |= PTP_SERIAL_TOD_IFACE_LS_AUTO_CLR; in __vsc8584_init_ptp()
1434 val); in __vsc8584_init_ptp()
1439 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1441 val &= ~(PTP_EGR_TS_FIFO_SIG_BYTES_MASK | PTP_EGR_TS_FIFO_THRESH_MASK); in __vsc8584_init_ptp()
1443 val |= PTP_EGR_TS_FIFO_SIG_BYTES(16) | PTP_EGR_TS_FIFO_THRESH(7); in __vsc8584_init_ptp()
1445 val); in __vsc8584_init_ptp()
1449 val = PTP_IFACE_CTRL_CLK_ENA; in __vsc8584_init_ptp()
1451 val |= PTP_IFACE_CTRL_GMII_PROT; in __vsc8584_init_ptp()
1452 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in __vsc8584_init_ptp()
1456 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_VERSION_CODE); in __vsc8584_init_ptp()
1458 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL); in __vsc8584_init_ptp()
1459 val |= PTP_IFACE_CTRL_EGR_BYPASS; in __vsc8584_init_ptp()
1460 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in __vsc8584_init_ptp()
1465 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, in __vsc8584_init_ptp()
1468 val &= ~(PTP_ANALYZER_MODE_EGR_ENA_MASK | in __vsc8584_init_ptp()
1475 val |= PTP_ANA_SPLIT_ENCAP_FLOW | PTP_ANA_INGR_ENCAP_FLOW_MODE(0x7) | in __vsc8584_init_ptp()
1478 val); in __vsc8584_init_ptp()