Lines Matching refs:phydev
18 static bool genphy_c45_baset1_able(struct phy_device *phydev) in genphy_c45_baset1_able() argument
22 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
23 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); in genphy_c45_baset1_able()
27 phydev->pma_extable = val; in genphy_c45_baset1_able()
30 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
37 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) in genphy_c45_pma_can_sleep() argument
41 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); in genphy_c45_pma_can_sleep()
52 int genphy_c45_pma_resume(struct phy_device *phydev) in genphy_c45_pma_resume() argument
54 if (!genphy_c45_pma_can_sleep(phydev)) in genphy_c45_pma_resume()
57 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_resume()
66 int genphy_c45_pma_suspend(struct phy_device *phydev) in genphy_c45_pma_suspend() argument
68 if (!genphy_c45_pma_can_sleep(phydev)) in genphy_c45_pma_suspend()
71 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_suspend()
81 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev) in genphy_c45_pma_baset1_setup_master_slave() argument
85 switch (phydev->master_slave_set) { in genphy_c45_pma_baset1_setup_master_slave()
97 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); in genphy_c45_pma_baset1_setup_master_slave()
101 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, in genphy_c45_pma_baset1_setup_master_slave()
110 int genphy_c45_pma_setup_forced(struct phy_device *phydev) in genphy_c45_pma_setup_forced() argument
115 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
118 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_pma_setup_forced()
122 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); in genphy_c45_pma_setup_forced()
133 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
135 if (genphy_c45_baset1_able(phydev)) in genphy_c45_pma_setup_forced()
168 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced()
172 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); in genphy_c45_pma_setup_forced()
176 if (genphy_c45_baset1_able(phydev)) { in genphy_c45_pma_setup_forced()
177 ret = genphy_c45_pma_baset1_setup_master_slave(phydev); in genphy_c45_pma_setup_forced()
182 if (phydev->speed == SPEED_1000) in genphy_c45_pma_setup_forced()
185 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, in genphy_c45_pma_setup_forced()
191 return genphy_c45_an_disable_aneg(phydev); in genphy_c45_pma_setup_forced()
203 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev) in genphy_c45_baset1_an_config_aneg() argument
215 switch (phydev->master_slave_set) { in genphy_c45_baset1_an_config_aneg()
234 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); in genphy_c45_baset1_an_config_aneg()
238 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
240 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, in genphy_c45_baset1_an_config_aneg()
247 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
249 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, in genphy_c45_baset1_an_config_aneg()
268 int genphy_c45_an_config_aneg(struct phy_device *phydev) in genphy_c45_an_config_aneg() argument
273 linkmode_and(phydev->advertising, phydev->advertising, in genphy_c45_an_config_aneg()
274 phydev->supported); in genphy_c45_an_config_aneg()
276 ret = genphy_c45_an_config_eee_aneg(phydev); in genphy_c45_an_config_aneg()
282 if (genphy_c45_baset1_able(phydev)) in genphy_c45_an_config_aneg()
283 return genphy_c45_baset1_an_config_aneg(phydev); in genphy_c45_an_config_aneg()
285 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
287 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, in genphy_c45_an_config_aneg()
296 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
298 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_an_config_aneg()
320 int genphy_c45_an_disable_aneg(struct phy_device *phydev) in genphy_c45_an_disable_aneg() argument
324 if (genphy_c45_baset1_able(phydev)) in genphy_c45_an_disable_aneg()
327 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_an_disable_aneg()
340 int genphy_c45_restart_aneg(struct phy_device *phydev) in genphy_c45_restart_aneg() argument
344 if (genphy_c45_baset1_able(phydev)) in genphy_c45_restart_aneg()
347 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_restart_aneg()
361 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) in genphy_c45_check_and_restart_aneg() argument
366 if (genphy_c45_baset1_able(phydev)) in genphy_c45_check_and_restart_aneg()
371 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_check_and_restart_aneg()
380 return genphy_c45_restart_aneg(phydev); in genphy_c45_check_and_restart_aneg()
397 int genphy_c45_aneg_done(struct phy_device *phydev) in genphy_c45_aneg_done() argument
402 if (genphy_c45_baset1_able(phydev)) in genphy_c45_aneg_done()
405 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_aneg_done()
419 int genphy_c45_read_link(struct phy_device *phydev) in genphy_c45_read_link() argument
425 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_read_link()
426 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
434 phydev->link = 0; in genphy_c45_read_link()
448 if (!phy_polling_mode(phydev) || !phydev->link) { in genphy_c45_read_link()
449 val = phy_read_mmd(phydev, devad, MDIO_STAT1); in genphy_c45_read_link()
456 val = phy_read_mmd(phydev, devad, MDIO_STAT1); in genphy_c45_read_link()
464 phydev->link = link; in genphy_c45_read_link()
475 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev) in genphy_c45_baset1_read_lpa() argument
479 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); in genphy_c45_baset1_read_lpa()
484 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); in genphy_c45_baset1_read_lpa()
485 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
486 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
488 phydev->pause = 0; in genphy_c45_baset1_read_lpa()
489 phydev->asym_pause = 0; in genphy_c45_baset1_read_lpa()
494 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); in genphy_c45_baset1_read_lpa()
496 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L); in genphy_c45_baset1_read_lpa()
500 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
501 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0; in genphy_c45_baset1_read_lpa()
502 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0; in genphy_c45_baset1_read_lpa()
504 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M); in genphy_c45_baset1_read_lpa()
508 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
523 int genphy_c45_read_lpa(struct phy_device *phydev) in genphy_c45_read_lpa() argument
527 if (genphy_c45_baset1_able(phydev)) in genphy_c45_read_lpa()
528 return genphy_c45_baset1_read_lpa(phydev); in genphy_c45_read_lpa()
530 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_read_lpa()
536 phydev->lp_advertising); in genphy_c45_read_lpa()
537 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
538 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
539 phydev->pause = 0; in genphy_c45_read_lpa()
540 phydev->asym_pause = 0; in genphy_c45_read_lpa()
545 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, in genphy_c45_read_lpa()
549 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); in genphy_c45_read_lpa()
553 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
554 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; in genphy_c45_read_lpa()
555 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; in genphy_c45_read_lpa()
558 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in genphy_c45_read_lpa()
562 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
573 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev) in genphy_c45_pma_baset1_read_master_slave() argument
577 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
578 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
580 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL); in genphy_c45_pma_baset1_read_master_slave()
585 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_pma_baset1_read_master_slave()
586 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in genphy_c45_pma_baset1_read_master_slave()
588 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_pma_baset1_read_master_slave()
589 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in genphy_c45_pma_baset1_read_master_slave()
600 int genphy_c45_read_pma(struct phy_device *phydev) in genphy_c45_read_pma() argument
604 linkmode_zero(phydev->lp_advertising); in genphy_c45_read_pma()
606 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_read_pma()
612 phydev->speed = SPEED_10; in genphy_c45_read_pma()
615 phydev->speed = SPEED_100; in genphy_c45_read_pma()
618 phydev->speed = SPEED_1000; in genphy_c45_read_pma()
621 phydev->speed = SPEED_2500; in genphy_c45_read_pma()
624 phydev->speed = SPEED_5000; in genphy_c45_read_pma()
627 phydev->speed = SPEED_10000; in genphy_c45_read_pma()
630 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_pma()
634 phydev->duplex = DUPLEX_FULL; in genphy_c45_read_pma()
636 if (genphy_c45_baset1_able(phydev)) { in genphy_c45_read_pma()
637 val = genphy_c45_pma_baset1_read_master_slave(phydev); in genphy_c45_read_pma()
650 int genphy_c45_read_mdix(struct phy_device *phydev) in genphy_c45_read_mdix() argument
654 if (phydev->speed == SPEED_10000) { in genphy_c45_read_mdix()
655 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in genphy_c45_read_mdix()
662 phydev->mdix = ETH_TP_MDI; in genphy_c45_read_mdix()
666 phydev->mdix = ETH_TP_MDI_X; in genphy_c45_read_mdix()
670 phydev->mdix = ETH_TP_MDI_INVALID; in genphy_c45_read_mdix()
684 static int genphy_c45_write_eee_adv(struct phy_device *phydev, in genphy_c45_write_eee_adv() argument
689 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_write_eee_adv()
695 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
707 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_write_eee_adv()
713 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
724 phydev->supported_eee)) { in genphy_c45_write_eee_adv()
729 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
747 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv) in genphy_c45_read_eee_adv() argument
751 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_adv()
755 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV); in genphy_c45_read_eee_adv()
762 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_read_eee_adv()
766 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2); in genphy_c45_read_eee_adv()
774 phydev->supported_eee)) { in genphy_c45_read_eee_adv()
778 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL); in genphy_c45_read_eee_adv()
793 static int genphy_c45_read_eee_lpa(struct phy_device *phydev, in genphy_c45_read_eee_lpa() argument
798 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_lpa()
802 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); in genphy_c45_read_eee_lpa()
809 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_read_eee_lpa()
813 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2); in genphy_c45_read_eee_lpa()
821 phydev->supported_eee)) { in genphy_c45_read_eee_lpa()
825 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT); in genphy_c45_read_eee_lpa()
839 static int genphy_c45_read_eee_cap1(struct phy_device *phydev) in genphy_c45_read_eee_cap1() argument
846 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); in genphy_c45_read_eee_cap1()
858 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val); in genphy_c45_read_eee_cap1()
863 linkmode_and(phydev->supported_eee, phydev->supported_eee, in genphy_c45_read_eee_cap1()
864 phydev->supported); in genphy_c45_read_eee_cap1()
873 static int genphy_c45_read_eee_cap2(struct phy_device *phydev) in genphy_c45_read_eee_cap2() argument
880 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2); in genphy_c45_read_eee_cap2()
888 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val); in genphy_c45_read_eee_cap2()
897 int genphy_c45_read_eee_abilities(struct phy_device *phydev) in genphy_c45_read_eee_abilities() argument
905 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_abilities()
906 val = genphy_c45_read_eee_cap1(phydev); in genphy_c45_read_eee_abilities()
912 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_read_eee_abilities()
913 val = genphy_c45_read_eee_cap2(phydev); in genphy_c45_read_eee_abilities()
919 phydev->supported)) { in genphy_c45_read_eee_abilities()
923 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT); in genphy_c45_read_eee_abilities()
928 phydev->supported_eee, in genphy_c45_read_eee_abilities()
940 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev) in genphy_c45_an_config_eee_aneg() argument
942 if (!phydev->eee_cfg.eee_enabled) { in genphy_c45_an_config_eee_aneg()
945 return genphy_c45_write_eee_adv(phydev, adv); in genphy_c45_an_config_eee_aneg()
948 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee); in genphy_c45_an_config_eee_aneg()
958 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev) in genphy_c45_pma_baset1_read_abilities() argument
962 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1); in genphy_c45_pma_baset1_read_abilities()
967 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
971 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
975 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
978 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); in genphy_c45_pma_baset1_read_abilities()
983 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
997 int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev) in genphy_c45_pma_read_ext_abilities() argument
1001 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); in genphy_c45_pma_read_ext_abilities()
1006 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1009 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1012 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1015 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1018 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1021 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1025 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1028 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1032 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1035 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1039 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in genphy_c45_pma_read_ext_abilities()
1045 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1049 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1054 val = genphy_c45_pma_baset1_read_abilities(phydev); in genphy_c45_pma_read_ext_abilities()
1074 int genphy_c45_pma_read_abilities(struct phy_device *phydev) in genphy_c45_pma_read_abilities() argument
1078 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); in genphy_c45_pma_read_abilities()
1079 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_pma_read_abilities()
1080 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_pma_read_abilities()
1086 phydev->supported); in genphy_c45_pma_read_abilities()
1089 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); in genphy_c45_pma_read_abilities()
1094 phydev->supported, in genphy_c45_pma_read_abilities()
1098 phydev->supported, in genphy_c45_pma_read_abilities()
1102 phydev->supported, in genphy_c45_pma_read_abilities()
1106 val = genphy_c45_pma_read_ext_abilities(phydev); in genphy_c45_pma_read_abilities()
1114 genphy_c45_read_eee_abilities(phydev); in genphy_c45_pma_read_abilities()
1126 int genphy_c45_baset1_read_status(struct phy_device *phydev) in genphy_c45_baset1_read_status() argument
1131 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_baset1_read_status()
1132 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_baset1_read_status()
1134 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L); in genphy_c45_baset1_read_status()
1138 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M); in genphy_c45_baset1_read_status()
1144 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_baset1_read_status()
1146 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_baset1_read_status()
1149 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; in genphy_c45_baset1_read_status()
1151 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; in genphy_c45_baset1_read_status()
1164 int genphy_c45_read_status(struct phy_device *phydev) in genphy_c45_read_status() argument
1168 ret = genphy_c45_read_link(phydev); in genphy_c45_read_status()
1172 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_status()
1173 phydev->duplex = DUPLEX_UNKNOWN; in genphy_c45_read_status()
1174 phydev->pause = 0; in genphy_c45_read_status()
1175 phydev->asym_pause = 0; in genphy_c45_read_status()
1177 if (phydev->autoneg == AUTONEG_ENABLE) { in genphy_c45_read_status()
1178 ret = genphy_c45_read_lpa(phydev); in genphy_c45_read_status()
1182 if (genphy_c45_baset1_able(phydev)) { in genphy_c45_read_status()
1183 ret = genphy_c45_baset1_read_status(phydev); in genphy_c45_read_status()
1188 phy_resolve_aneg_linkmode(phydev); in genphy_c45_read_status()
1190 ret = genphy_c45_read_pma(phydev); in genphy_c45_read_status()
1205 int genphy_c45_config_aneg(struct phy_device *phydev) in genphy_c45_config_aneg() argument
1210 if (phydev->autoneg == AUTONEG_DISABLE) in genphy_c45_config_aneg()
1211 return genphy_c45_pma_setup_forced(phydev); in genphy_c45_config_aneg()
1213 ret = genphy_c45_an_config_aneg(phydev); in genphy_c45_config_aneg()
1219 return genphy_c45_check_and_restart_aneg(phydev, changed); in genphy_c45_config_aneg()
1225 int gen10g_config_aneg(struct phy_device *phydev) in gen10g_config_aneg() argument
1231 int genphy_c45_loopback(struct phy_device *phydev, bool enable, int speed) in genphy_c45_loopback() argument
1236 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, in genphy_c45_loopback()
1252 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) in genphy_c45_fast_retrain() argument
1257 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()
1260 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { in genphy_c45_fast_retrain()
1261 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_fast_retrain()
1266 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, in genphy_c45_fast_retrain()
1272 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()
1286 int genphy_c45_plca_get_cfg(struct phy_device *phydev, in genphy_c45_plca_get_cfg() argument
1291 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); in genphy_c45_plca_get_cfg()
1300 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); in genphy_c45_plca_get_cfg()
1306 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); in genphy_c45_plca_get_cfg()
1313 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); in genphy_c45_plca_get_cfg()
1319 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); in genphy_c45_plca_get_cfg()
1340 int genphy_c45_plca_set_cfg(struct phy_device *phydev, in genphy_c45_plca_set_cfg() argument
1352 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1367 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1384 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1392 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1407 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1424 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1433 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1454 int genphy_c45_plca_get_status(struct phy_device *phydev, in genphy_c45_plca_get_status() argument
1459 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS); in genphy_c45_plca_get_status()
1476 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *lp) in genphy_c45_eee_is_active() argument
1482 if (!phydev->eee_cfg.eee_enabled) in genphy_c45_eee_is_active()
1485 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp); in genphy_c45_eee_is_active()
1492 linkmode_and(common, phydev->advertising_eee, tmp_lp); in genphy_c45_eee_is_active()
1496 return phy_check_valid(phydev->speed, phydev->duplex, common); in genphy_c45_eee_is_active()
1508 int genphy_c45_ethtool_get_eee(struct phy_device *phydev, in genphy_c45_ethtool_get_eee() argument
1513 ret = genphy_c45_eee_is_active(phydev, data->lp_advertised); in genphy_c45_ethtool_get_eee()
1517 data->eee_active = phydev->eee_active; in genphy_c45_ethtool_get_eee()
1518 linkmode_andnot(data->supported, phydev->supported_eee, in genphy_c45_ethtool_get_eee()
1519 phydev->eee_disabled_modes); in genphy_c45_ethtool_get_eee()
1520 linkmode_copy(data->advertised, phydev->advertising_eee); in genphy_c45_ethtool_get_eee()
1538 int genphy_c45_ethtool_set_eee(struct phy_device *phydev, in genphy_c45_ethtool_set_eee() argument
1549 if (linkmode_andnot(tmp, adv, phydev->supported_eee)) { in genphy_c45_ethtool_set_eee()
1550 phydev_warn(phydev, "At least some EEE link modes are not supported.\n"); in genphy_c45_ethtool_set_eee()
1554 linkmode_andnot(phydev->advertising_eee, adv, in genphy_c45_ethtool_set_eee()
1555 phydev->eee_disabled_modes); in genphy_c45_ethtool_set_eee()
1556 } else if (linkmode_empty(phydev->advertising_eee)) { in genphy_c45_ethtool_set_eee()
1557 phy_advertise_eee_all(phydev); in genphy_c45_ethtool_set_eee()
1561 ret = genphy_c45_an_config_eee_aneg(phydev); in genphy_c45_ethtool_set_eee()
1563 ret = phy_restart_aneg(phydev); in genphy_c45_ethtool_set_eee()