Lines Matching refs:htt
3605 lockdep_assert_held(&ar->htt.tx_lock); in ath10k_mac_tx_lock()
3626 lockdep_assert_held(&ar->htt.tx_lock); in ath10k_mac_tx_unlock()
3646 lockdep_assert_held(&ar->htt.tx_lock); in ath10k_mac_vif_tx_lock()
3657 lockdep_assert_held(&ar->htt.tx_lock); in ath10k_mac_vif_tx_unlock()
3677 lockdep_assert_held(&ar->htt.tx_lock); in ath10k_mac_vif_handle_tx_pause()
3722 spin_lock_bh(&ar->htt.tx_lock); in ath10k_mac_handle_tx_pause_vdev()
3727 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_mac_handle_tx_pause_vdev()
3765 if (ar->htt.target_version_major < 3 && in ath10k_mac_tx_h_get_txmode()
3967 return (ar->htt.target_version_major >= 3 && in ath10k_mac_tx_frm_has_freq()
3968 ar->htt.target_version_minor >= 4 && in ath10k_mac_tx_frm_has_freq()
4003 else if (ar->htt.target_version_major >= 3) in ath10k_mac_tx_h_get_txpath()
4017 struct ath10k_htt *htt = &ar->htt; in ath10k_mac_tx_submit() local
4022 ret = ath10k_htt_tx(htt, txmode, skb); in ath10k_mac_tx_submit()
4025 ret = ath10k_htt_mgmt_tx(htt, skb); in ath10k_mac_tx_submit()
4295 spin_lock_bh(&ar->htt.tx_lock); in ath10k_mac_txq_unref()
4296 idr_for_each_entry(&ar->htt.pending_tx, msdu, msdu_id) { in ath10k_mac_txq_unref()
4301 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_mac_txq_unref()
4334 if (ar->htt.tx_q_state.mode == HTT_TX_MODE_SWITCH_PUSH) in ath10k_mac_tx_can_push()
4337 if (ar->htt.num_pending_tx < ar->htt.tx_q_state.num_push_allowed) in ath10k_mac_tx_can_push()
4396 struct ath10k_htt *htt = &ar->htt; in ath10k_mac_tx_push_txq() local
4409 spin_lock_bh(&ar->htt.tx_lock); in ath10k_mac_tx_push_txq()
4410 ret = ath10k_htt_tx_inc_pending(htt); in ath10k_mac_tx_push_txq()
4411 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_mac_tx_push_txq()
4418 spin_lock_bh(&ar->htt.tx_lock); in ath10k_mac_tx_push_txq()
4419 ath10k_htt_tx_dec_pending(htt); in ath10k_mac_tx_push_txq()
4420 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_mac_tx_push_txq()
4437 spin_lock_bh(&ar->htt.tx_lock); in ath10k_mac_tx_push_txq()
4438 ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp); in ath10k_mac_tx_push_txq()
4441 ath10k_htt_tx_dec_pending(htt); in ath10k_mac_tx_push_txq()
4442 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_mac_tx_push_txq()
4445 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_mac_tx_push_txq()
4452 spin_lock_bh(&ar->htt.tx_lock); in ath10k_mac_tx_push_txq()
4453 ath10k_htt_tx_dec_pending(htt); in ath10k_mac_tx_push_txq()
4455 ath10k_htt_tx_mgmt_dec_pending(htt); in ath10k_mac_tx_push_txq()
4456 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_mac_tx_push_txq()
4461 spin_lock_bh(&ar->htt.tx_lock); in ath10k_mac_tx_push_txq()
4463 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_mac_tx_push_txq()
4495 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH) in ath10k_mac_tx_push_pending()
4498 if (ar->htt.num_pending_tx >= (ar->htt.max_num_pending_tx / 2)) in ath10k_mac_tx_push_pending()
4684 struct ath10k_htt *htt = &ar->htt; in ath10k_mac_op_tx() local
4708 spin_lock_bh(&ar->htt.tx_lock); in ath10k_mac_op_tx()
4715 ret = ath10k_htt_tx_inc_pending(htt); in ath10k_mac_op_tx()
4719 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_mac_op_tx()
4724 ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp); in ath10k_mac_op_tx()
4728 ath10k_htt_tx_dec_pending(htt); in ath10k_mac_op_tx()
4729 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_mac_op_tx()
4733 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_mac_op_tx()
4740 spin_lock_bh(&ar->htt.tx_lock); in ath10k_mac_op_tx()
4741 ath10k_htt_tx_dec_pending(htt); in ath10k_mac_op_tx()
4743 ath10k_htt_tx_mgmt_dec_pending(htt); in ath10k_mac_op_tx()
4744 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_mac_op_tx()
4758 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH) in ath10k_mac_op_wake_tx_queue()
5874 spin_lock_bh(&ar->htt.tx_lock); in ath10k_add_interface()
5877 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_add_interface()
6021 spin_lock_bh(&ar->htt.tx_lock); in ath10k_remove_interface()
6023 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_remove_interface()
8094 time_left = wait_event_timeout(ar->htt.empty_tx_wq, ({ in ath10k_mac_wait_tx_complete()
8097 spin_lock_bh(&ar->htt.tx_lock); in ath10k_mac_wait_tx_complete()
8098 empty = (ar->htt.num_pending_tx == 0); in ath10k_mac_wait_tx_complete()
8099 spin_unlock_bh(&ar->htt.tx_lock); in ath10k_mac_wait_tx_complete()
8128 ath10k_htt_flush_tx(&ar->htt); in ath10k_flush()
9384 if (ar->htt.disable_tx_comp) { in ath10k_sta_statistics()