Lines Matching refs:b43_phy_write
205 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0); in lpphy_baseband_rev0_1_init()
206 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0); in lpphy_baseband_rev0_1_init()
207 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0); in lpphy_baseband_rev0_1_init()
208 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0); in lpphy_baseband_rev0_1_init()
212 b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016); in lpphy_baseband_rev0_1_init()
245 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp); in lpphy_baseband_rev0_1_init()
312 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005); in lpphy_baseband_rev0_1_init()
313 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF); in lpphy_baseband_rev0_1_init()
334 b43_phy_write(dev, B43_LPPHY_4C3, tmp2); in lpphy_baseband_rev0_1_init()
338 b43_phy_write(dev, B43_LPPHY_4C4, tmp2); in lpphy_baseband_rev0_1_init()
342 b43_phy_write(dev, B43_LPPHY_4C5, tmp2); in lpphy_baseband_rev0_1_init()
371 b43_phy_write(dev, addr[i], coefs[i]); in lpphy_save_dig_flt_state()
393 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]); in lpphy_restore_dig_flt_state()
400 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50); in lpphy_baseband_rev2plus_init()
401 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800); in lpphy_baseband_rev2plus_init()
402 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0); in lpphy_baseband_rev2plus_init()
403 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0); in lpphy_baseband_rev2plus_init()
404 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0); in lpphy_baseband_rev2plus_init()
405 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0); in lpphy_baseband_rev2plus_init()
406 b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0); in lpphy_baseband_rev2plus_init()
407 b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0); in lpphy_baseband_rev2plus_init()
425 b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48); in lpphy_baseband_rev2plus_init()
471 b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80); in lpphy_baseband_rev2plus_init()
472 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954); in lpphy_baseband_rev2plus_init()
473 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1, in lpphy_baseband_rev2plus_init()
680 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80); in lpphy_radio_init()
681 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0); in lpphy_radio_init()
772 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0); in lpphy_disable_crs()
773 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1); in lpphy_disable_crs()
774 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20); in lpphy_disable_crs()
777 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0); in lpphy_disable_crs()
778 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF); in lpphy_disable_crs()
779 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF); in lpphy_disable_crs()
896 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, in lpphy_set_tx_gains()
904 b43_phy_write(dev, B43_PHY_OFDM(0xFC), in lpphy_set_tx_gains()
924 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna); in lpphy_rev0_1_set_rx_gain()
940 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain); in lpphy_rev2plus_set_rx_gain()
993 b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples); in lpphy_rx_iq_est()
1248 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval); in lpphy_rev0_1_rc_calib()
1249 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr); in lpphy_rev0_1_rc_calib()
1250 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval); in lpphy_rev0_1_rc_calib()
1251 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr); in lpphy_rev0_1_rc_calib()
1252 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval); in lpphy_rev0_1_rc_calib()
1253 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr); in lpphy_rev0_1_rc_calib()
1254 b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl); in lpphy_rev0_1_rc_calib()
1505 b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA); in lpphy_tx_pctl_init_hw()