Lines Matching refs:slot_ctrl
140 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE && in pcie_wait_cmd()
141 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE) in pcie_wait_cmd()
148 ctrl->slot_ctrl, in pcie_wait_cmd()
161 u16 slot_ctrl_orig, slot_ctrl; in pcie_do_write_cmd() local
170 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); in pcie_do_write_cmd()
171 if (PCI_POSSIBLE_ERROR(slot_ctrl)) { in pcie_do_write_cmd()
176 slot_ctrl_orig = slot_ctrl; in pcie_do_write_cmd()
177 slot_ctrl &= ~mask; in pcie_do_write_cmd()
178 slot_ctrl |= (cmd & mask); in pcie_do_write_cmd()
181 ctrl->slot_ctrl = slot_ctrl; in pcie_do_write_cmd()
182 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); in pcie_do_write_cmd()
193 (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK)) in pcie_do_write_cmd()
355 u16 slot_ctrl; in pciehp_get_raw_indicator_status() local
358 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); in pciehp_get_raw_indicator_status()
360 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6; in pciehp_get_raw_indicator_status()
368 u16 slot_ctrl; in pciehp_get_attention_status() local
371 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); in pciehp_get_attention_status()
374 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); in pciehp_get_attention_status()
376 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { in pciehp_get_attention_status()
397 u16 slot_ctrl; in pciehp_get_power_status() local
399 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); in pciehp_get_power_status()
401 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); in pciehp_get_power_status()
403 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { in pciehp_get_power_status()
634 (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode)) in pciehp_isr()