Lines Matching refs:pmu_base
130 #define CMN_DT_PMEVCNT(dtc, n) ((dtc)->pmu_base + _CMN_DT_CNT_REG(n))
131 #define CMN_DT_PMCCNTR(dtc) ((dtc)->pmu_base + 0x40)
133 #define CMN_DT_PMEVCNTSR(dtc, n) ((dtc)->pmu_base + 0x50 + _CMN_DT_CNT_REG(n))
134 #define CMN_DT_PMCCNTRSR(dtc) ((dtc)->pmu_base + 0x90)
136 #define CMN_DT_PMCR(dtc) ((dtc)->pmu_base + 0x100)
141 #define CMN_DT_PMOVSR(dtc) ((dtc)->pmu_base + 0x118)
142 #define CMN_DT_PMOVSR_CLR(dtc) ((dtc)->pmu_base + 0x120)
144 #define CMN_DT_PMSSR(dtc) ((dtc)->pmu_base + 0x128)
147 #define CMN_DT_PMSRR(dtc) ((dtc)->pmu_base + 0x130)
283 void __iomem *pmu_base; member
317 void __iomem *pmu_base; member
451 return readl_relaxed(xp->pmu_base + offset); in arm_cmn_device_connect_info()
1542 writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4); in arm_cmn_set_event_sel_hi()
1555 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL); in arm_cmn_set_event_sel_lo()
1558 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL); in arm_cmn_set_event_sel_lo()
1582 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); in arm_cmn_event_start()
1611 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset); in arm_cmn_event_stop()
2118 dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx); in arm_cmn_init_dtm()
2132 dtc->pmu_base = dn->pmu_base; in arm_cmn_init_dtc()
2133 dtc->base = dtc->pmu_base - arm_cmn_pmu_offset(cmn, dn); in arm_cmn_init_dtc()
2220 node->pmu_base = cmn->base + offset + arm_cmn_pmu_offset(cmn, node); in arm_cmn_init_node_info()
2440 dn->pmu_base += CMN_CCLA_PMU_EVENT_SEL; in arm_cmn_discover()
2461 dn[0].pmu_base += CMN_CCLA_PMU_EVENT_SEL; in arm_cmn_discover()