Lines Matching refs:mtk_phy_set_bits
592 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL); in u3_phy_params_write()
597 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL); in u3_phy_params_write()
702 mtk_phy_set_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN); in hs_slew_rate_calibrate()
706 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); in hs_slew_rate_calibrate()
718 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); in hs_slew_rate_calibrate()
763 mtk_phy_set_bits(phyd + U3P_U3_PHYD_TOP1, P3D_RG_FORCE_PHY_MODE); in u3_phy_instance_init()
765 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD, in u3_phy_instance_init()
767 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE, in u3_phy_instance_init()
778 mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3, in u3_phy_instance_init()
817 mtk_phy_set_bits(com + U3P_U2PHYA_RESV1, in u2_phy_pll_26m_set()
836 mtk_phy_set_bits(com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN); in u2_phy_instance_init()
845 mtk_phy_set_bits(com + U3P_USBPHYACR2, PA2_RG_SIF_U2PLL_FORCE_EN); in u2_phy_instance_init()
849 mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); in u2_phy_instance_init()
851 mtk_phy_set_bits(com + U3P_U2PHYDTM0, in u2_phy_instance_init()
875 mtk_phy_set_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN); in u2_phy_instance_power_on()
877 mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID); in u2_phy_instance_power_on()
882 mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); in u2_phy_instance_power_on()
884 mtk_phy_set_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); in u2_phy_instance_power_on()
901 mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND); in u2_phy_instance_power_off()
1019 mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD, in pcie_phy_instance_power_off()
1022 mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE, in pcie_phy_instance_power_off()
1162 mtk_phy_set_bits(com + U3P_U2PHYBC12C, P2C_RG_CHGDT_EN); in u2_phy_props_set()
1178 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, in u2_phy_props_set()
1338 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS); in phy_efuse_set()
1345 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS); in phy_efuse_set()
1349 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL); in phy_efuse_set()
1353 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL); in phy_efuse_set()