Lines Matching refs:pbase
124 void __iomem *pbase = inst->port_base; in u2_phy_slew_rate_calibrate() local
134 mtk_phy_set_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN); in u2_phy_slew_rate_calibrate()
138 mtk_phy_set_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); in u2_phy_slew_rate_calibrate()
141 mtk_phy_update_field(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT, in u2_phy_slew_rate_calibrate()
145 mtk_phy_set_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); in u2_phy_slew_rate_calibrate()
148 readl_poll_timeout(pbase + XSP_U2FREQ_FMMONR1, tmp, in u2_phy_slew_rate_calibrate()
151 fm_out = readl(pbase + XSP_U2FREQ_MMONR0); in u2_phy_slew_rate_calibrate()
154 mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); in u2_phy_slew_rate_calibrate()
157 mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); in u2_phy_slew_rate_calibrate()
173 mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, calib_val); in u2_phy_slew_rate_calibrate()
176 mtk_phy_clear_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN); in u2_phy_slew_rate_calibrate()
182 void __iomem *pbase = inst->port_base; in u2_phy_instance_init() local
185 mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_BC11_SW_EN); in u2_phy_instance_init()
187 mtk_phy_set_bits(pbase + XSP_USBPHYACR0, P2A0_RG_INTR_EN); in u2_phy_instance_init()
193 void __iomem *pbase = inst->port_base; in u2_phy_instance_power_on() local
196 mtk_phy_set_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN); in u2_phy_instance_power_on()
198 mtk_phy_update_bits(pbase + XSP_U2PHYDTM1, in u2_phy_instance_power_on()
208 void __iomem *pbase = inst->port_base; in u2_phy_instance_power_off() local
211 mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN); in u2_phy_instance_power_off()
213 mtk_phy_update_bits(pbase + XSP_U2PHYDTM1, in u2_phy_instance_power_off()
287 void __iomem *pbase = inst->port_base; in u2_phy_props_set() local
290 mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL, in u2_phy_props_set()
294 mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, in u2_phy_props_set()
298 mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL, in u2_phy_props_set()
302 mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL, in u2_phy_props_set()
309 void __iomem *pbase = inst->port_base; in u3_phy_props_set() local
316 mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_04, in u3_phy_props_set()
320 mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_14, in u3_phy_props_set()