Lines Matching refs:gctrl
28 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); in eqbr_gpio_disable_irq() local
32 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
33 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
34 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
41 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); in eqbr_gpio_enable_irq() local
47 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
48 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
49 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
55 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); in eqbr_gpio_ack_irq() local
59 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_ack_irq()
60 writel(BIT(offset), gctrl->membase + GPIO_IRNCR); in eqbr_gpio_ack_irq()
61 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_ack_irq()
80 struct eqbr_gpio_ctrl *gctrl, in eqbr_irq_type_cfg() argument
85 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_irq_type_cfg()
86 eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type); in eqbr_irq_type_cfg()
87 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type); in eqbr_irq_type_cfg()
88 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type); in eqbr_irq_type_cfg()
89 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_irq_type_cfg()
97 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); in eqbr_gpio_set_irq_type() local
141 eqbr_irq_type_cfg(&it, gctrl, offset); in eqbr_gpio_set_irq_type()
153 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); in eqbr_irq_handler() local
158 pins = readl(gctrl->membase + GPIO_IRNCR); in eqbr_irq_handler()
177 static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl) in gpiochip_setup() argument
182 gc = &gctrl->chip; in gpiochip_setup()
183 gc->label = gctrl->name; in gpiochip_setup()
184 gc->fwnode = gctrl->fwnode; in gpiochip_setup()
188 if (!fwnode_property_read_bool(gctrl->fwnode, "interrupt-controller")) { in gpiochip_setup()
190 gctrl->name); in gpiochip_setup()
194 girq = &gctrl->chip.irq; in gpiochip_setup()
204 girq->parents[0] = gctrl->virq; in gpiochip_setup()
212 struct eqbr_gpio_ctrl *gctrl; in gpiolib_reg() local
218 gctrl = drvdata->gpio_ctrls + i; in gpiolib_reg()
219 np = to_of_node(gctrl->fwnode); in gpiolib_reg()
221 gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i); in gpiolib_reg()
222 if (!gctrl->name) in gpiolib_reg()
230 gctrl->membase = devm_ioremap_resource(dev, &res); in gpiolib_reg()
231 if (IS_ERR(gctrl->membase)) in gpiolib_reg()
232 return PTR_ERR(gctrl->membase); in gpiolib_reg()
234 gctrl->virq = irq_of_parse_and_map(np, 0); in gpiolib_reg()
235 if (!gctrl->virq) { in gpiolib_reg()
237 gctrl->name); in gpiolib_reg()
240 raw_spin_lock_init(&gctrl->lock); in gpiolib_reg()
242 ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8, in gpiolib_reg()
243 gctrl->membase + GPIO_IN, in gpiolib_reg()
244 gctrl->membase + GPIO_OUTSET, in gpiolib_reg()
245 gctrl->membase + GPIO_OUTCLR, in gpiolib_reg()
246 gctrl->membase + GPIO_DIR, in gpiolib_reg()
253 ret = gpiochip_setup(dev, gctrl); in gpiolib_reg()
257 ret = devm_gpiochip_add_data(dev, &gctrl->chip, gctrl); in gpiolib_reg()
387 struct eqbr_gpio_ctrl *gctrl; in eqbr_pinconf_get() local
427 gctrl = get_gpio_ctrls_via_bank(pctl, bank); in eqbr_pinconf_get()
428 if (!gctrl) { in eqbr_pinconf_get()
434 val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset)); in eqbr_pinconf_get()
450 struct eqbr_gpio_ctrl *gctrl; in eqbr_pinconf_set() local
496 gctrl = get_gpio_ctrls_via_bank(pctl, bank); in eqbr_pinconf_set()
497 if (!gctrl) { in eqbr_pinconf_set()
502 gc = &gctrl->chip; in eqbr_pinconf_set()