Lines Matching refs:pctrl
296 void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
297 void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
298 u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
299 int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);
370 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, in rzg2l_pinctrl_get_variable_pin_cfg() argument
377 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { in rzg2l_pinctrl_get_variable_pin_cfg()
378 u64 cfg = pctrl->data->variable_pin_cfg[i]; in rzg2l_pinctrl_get_variable_pin_cfg()
480 static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) in rzg2l_pmc_writeb() argument
482 writeb(val, pctrl->base + offset); in rzg2l_pmc_writeb()
485 static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) in rzv2h_pmc_writeb() argument
487 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzv2h_pmc_writeb()
490 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
491 writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
492 writeb(val, pctrl->base + offset); in rzv2h_pmc_writeb()
493 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
496 static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl, in rzg2l_validate_pin() argument
503 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) in rzg2l_validate_pin()
506 data = pctrl->data->port_pin_configs[port]; in rzg2l_validate_pin()
513 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, in rzg2l_pinctrl_set_pfc_mode() argument
519 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
522 reg = readw(pctrl->base + PM(off)); in rzg2l_pinctrl_set_pfc_mode()
524 writew(reg, pctrl->base + PM(off)); in rzg2l_pinctrl_set_pfc_mode()
526 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); in rzg2l_pinctrl_set_pfc_mode()
529 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
530 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
533 reg = readl(pctrl->base + PFC(off)); in rzg2l_pinctrl_set_pfc_mode()
535 writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); in rzg2l_pinctrl_set_pfc_mode()
538 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
539 writeb(reg | BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
541 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); in rzg2l_pinctrl_set_pfc_mode()
543 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
550 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_set_mux() local
551 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_set_mux()
569 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; in rzg2l_pinctrl_set_mux()
573 ret = rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(pins[i]), pin); in rzg2l_pinctrl_set_mux()
577 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", in rzg2l_pinctrl_set_mux()
580 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); in rzg2l_pinctrl_set_mux()
613 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_dt_subnode_to_map() local
637 dev_err(pctrl->dev, "Invalid pins list in DT\n"); in rzg2l_dt_subnode_to_map()
647 dev_err(pctrl->dev, in rzg2l_dt_subnode_to_map()
657 dev_err(pctrl->dev, "DT node must contain a config\n"); in rzg2l_dt_subnode_to_map()
693 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
694 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), in rzg2l_dt_subnode_to_map()
696 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
714 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", in rzg2l_dt_subnode_to_map()
734 mutex_lock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
754 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
761 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); in rzg2l_dt_subnode_to_map()
768 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
797 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_dt_node_to_map() local
822 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); in rzg2l_dt_node_to_map()
831 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, in rzg2l_read_pin_config() argument
834 void __iomem *addr = pctrl->base + offset; in rzg2l_read_pin_config()
845 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, in rzg2l_rmw_pin_config() argument
848 void __iomem *addr = pctrl->base + offset; in rzg2l_rmw_pin_config()
858 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
861 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
880 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) in rzg2l_get_power_source() argument
882 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_get_power_source()
888 return pctrl->settings[pin].power_source; in rzg2l_get_power_source()
894 val = readb(pctrl->base + pwr_reg); in rzg2l_get_power_source()
908 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) in rzg2l_set_power_source() argument
910 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_set_power_source()
916 pctrl->settings[pin].power_source = ps; in rzg2l_set_power_source()
940 writeb(val, pctrl->base + pwr_reg); in rzg2l_set_power_source()
941 pctrl->settings[pin].power_source = ps; in rzg2l_set_power_source()
1015 static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, in rzg2l_ds_is_supported() argument
1019 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_ds_is_supported()
1047 static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzg2l_pin_to_oen_bit() argument
1049 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; in rzg2l_pin_to_oen_bit()
1053 if (pin > pctrl->data->hwcfg->oen_max_pin) in rzg2l_pin_to_oen_bit()
1068 static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzg2l_read_oen() argument
1072 bit = rzg2l_pin_to_oen_bit(pctrl, _pin); in rzg2l_read_oen()
1076 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); in rzg2l_read_oen()
1079 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) in rzg2l_write_oen() argument
1085 bit = rzg2l_pin_to_oen_bit(pctrl, _pin); in rzg2l_write_oen()
1089 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_write_oen()
1090 val = readb(pctrl->base + ETH_MODE); in rzg2l_write_oen()
1095 writeb(val, pctrl->base + ETH_MODE); in rzg2l_write_oen()
1096 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_write_oen()
1101 static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzg3s_pin_to_oen_bit() argument
1103 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; in rzg3s_pin_to_oen_bit()
1111 if (pin > pctrl->data->hwcfg->oen_max_pin) in rzg3s_pin_to_oen_bit()
1115 if (port == pctrl->data->hwcfg->oen_max_port) in rzg3s_pin_to_oen_bit()
1121 static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzg3s_oen_read() argument
1125 bit = rzg3s_pin_to_oen_bit(pctrl, _pin); in rzg3s_oen_read()
1129 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); in rzg3s_oen_read()
1132 static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) in rzg3s_oen_write() argument
1138 bit = rzg3s_pin_to_oen_bit(pctrl, _pin); in rzg3s_oen_write()
1142 spin_lock_irqsave(&pctrl->lock, flags); in rzg3s_oen_write()
1143 val = readb(pctrl->base + ETH_MODE); in rzg3s_oen_write()
1148 writeb(val, pctrl->base + ETH_MODE); in rzg3s_oen_write()
1149 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg3s_oen_write()
1219 static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzv2h_pin_to_oen_bit() argument
1224 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; in rzv2h_pin_to_oen_bit()
1236 static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzv2h_oen_read() argument
1240 bit = rzv2h_pin_to_oen_bit(pctrl, _pin); in rzv2h_oen_read()
1242 return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); in rzv2h_oen_read()
1245 static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) in rzv2h_oen_write() argument
1247 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzv2h_oen_write()
1253 bit = rzv2h_pin_to_oen_bit(pctrl, _pin); in rzv2h_oen_write()
1254 spin_lock_irqsave(&pctrl->lock, flags); in rzv2h_oen_write()
1255 val = readb(pctrl->base + PFC_OEN); in rzv2h_oen_write()
1261 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_oen_write()
1262 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); in rzv2h_oen_write()
1263 writeb(val, pctrl->base + PFC_OEN); in rzv2h_oen_write()
1264 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); in rzv2h_oen_write()
1265 spin_unlock_irqrestore(&pctrl->lock, flags); in rzv2h_oen_write()
1274 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_pinconf_get() local
1275 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_pinconf_get()
1276 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_get()
1295 if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) in rzg2l_pinctrl_pinconf_get()
1303 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); in rzg2l_pinctrl_pinconf_get()
1311 if (!pctrl->data->oen_read) in rzg2l_pinctrl_pinconf_get()
1313 arg = pctrl->data->oen_read(pctrl, _pin); in rzg2l_pinctrl_pinconf_get()
1319 ret = rzg2l_get_power_source(pctrl, _pin, cfg); in rzg2l_pinctrl_pinconf_get()
1329 arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK); in rzg2l_pinctrl_pinconf_get()
1338 arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK); in rzg2l_pinctrl_pinconf_get()
1339 ret = pctrl->data->hw_to_bias_param(arg); in rzg2l_pinctrl_pinconf_get()
1355 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
1372 ret = rzg2l_get_power_source(pctrl, _pin, cfg); in rzg2l_pinctrl_pinconf_get()
1376 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
1387 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
1397 arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK); in rzg2l_pinctrl_pinconf_get()
1408 arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK); in rzg2l_pinctrl_pinconf_get()
1417 arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
1434 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_pinconf_set() local
1435 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_set()
1436 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_pinconf_set()
1437 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; in rzg2l_pinctrl_pinconf_set()
1455 if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) in rzg2l_pinctrl_pinconf_set()
1468 rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); in rzg2l_pinctrl_pinconf_set()
1474 if (!pctrl->data->oen_write) in rzg2l_pinctrl_pinconf_set()
1476 ret = pctrl->data->oen_write(pctrl, _pin, !!arg); in rzg2l_pinctrl_pinconf_set()
1489 rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg); in rzg2l_pinctrl_pinconf_set()
1498 ret = pctrl->data->bias_param_to_hw(param); in rzg2l_pinctrl_pinconf_set()
1502 rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret); in rzg2l_pinctrl_pinconf_set()
1517 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); in rzg2l_pinctrl_pinconf_set()
1539 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); in rzg2l_pinctrl_pinconf_set()
1547 rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK, in rzg2l_pinctrl_pinconf_set()
1555 rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg); in rzg2l_pinctrl_pinconf_set()
1564 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg); in rzg2l_pinctrl_pinconf_set()
1573 if (settings.power_source != pctrl->settings[_pin].power_source) { in rzg2l_pinctrl_pinconf_set()
1579 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); in rzg2l_pinctrl_pinconf_set()
1585 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { in rzg2l_pinctrl_pinconf_set()
1590 ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, in rzg2l_pinctrl_pinconf_set()
1601 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val); in rzg2l_pinctrl_pinconf_set()
1602 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; in rzg2l_pinctrl_pinconf_set()
1685 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_request() local
1686 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_request()
1695 ret = rzg2l_validate_pin(pctrl, *pin_data, port, bit); in rzg2l_gpio_request()
1703 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_request()
1706 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_request()
1708 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off)); in rzg2l_gpio_request()
1710 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_request()
1715 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, in rzg2l_gpio_set_direction() argument
1718 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_set_direction()
1725 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
1727 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_set_direction()
1731 writew(reg16, pctrl->base + PM(off)); in rzg2l_gpio_set_direction()
1733 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
1738 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_get_direction() local
1739 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_get_direction()
1744 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { in rzg2l_gpio_get_direction()
1747 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_get_direction()
1759 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_direction_input() local
1761 rzg2l_gpio_set_direction(pctrl, offset, false); in rzg2l_gpio_direction_input()
1769 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_set() local
1770 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_set()
1777 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set()
1779 reg8 = readb(pctrl->base + P(off)); in rzg2l_gpio_set()
1782 writeb(reg8 | BIT(bit), pctrl->base + P(off)); in rzg2l_gpio_set()
1784 writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); in rzg2l_gpio_set()
1786 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set()
1794 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_direction_output() local
1797 rzg2l_gpio_set_direction(pctrl, offset, true); in rzg2l_gpio_direction_output()
1804 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_get() local
1805 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_get()
1811 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_get()
1815 return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); in rzg2l_gpio_get()
1817 return !!(readb(pctrl->base + P(off)) & BIT(bit)); in rzg2l_gpio_get()
2419 static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) in rzg2l_gpio_get_gpioint() argument
2421 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; in rzg2l_gpio_get_gpioint()
2422 const struct rzg2l_pinctrl_data *data = pctrl->data; in rzg2l_gpio_get_gpioint()
2445 static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, in rzg2l_gpio_irq_endisable() argument
2448 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; in rzg2l_gpio_irq_endisable()
2455 addr = pctrl->base + ISEL(off); in rzg2l_gpio_irq_endisable()
2461 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_endisable()
2466 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_endisable()
2507 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); in rzg2l_gpio_irq_set_wake() local
2519 atomic_inc(&pctrl->wakeup_path); in rzg2l_gpio_irq_set_wake()
2521 atomic_dec(&pctrl->wakeup_path); in rzg2l_gpio_irq_set_wake()
2543 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_interrupt_input_mode() local
2544 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_interrupt_input_mode()
2551 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_interrupt_input_mode()
2567 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); in rzg2l_gpio_child_to_parent_hwirq() local
2572 gpioint = rzg2l_gpio_get_gpioint(child, pctrl); in rzg2l_gpio_child_to_parent_hwirq()
2580 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
2581 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); in rzg2l_gpio_child_to_parent_hwirq()
2582 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
2588 rzg2l_gpio_irq_endisable(pctrl, child, true); in rzg2l_gpio_child_to_parent_hwirq()
2589 pctrl->hwirq[irq] = child; in rzg2l_gpio_child_to_parent_hwirq()
2590 irq += pctrl->data->hwcfg->tint_start_index; in rzg2l_gpio_child_to_parent_hwirq()
2602 static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) in rzg2l_gpio_irq_restore() argument
2604 struct irq_domain *domain = pctrl->gpio_chip.irq.domain; in rzg2l_gpio_irq_restore()
2612 if (!pctrl->hwirq[i]) in rzg2l_gpio_irq_restore()
2615 virq = irq_find_mapping(domain, pctrl->hwirq[i]); in rzg2l_gpio_irq_restore()
2617 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", in rzg2l_gpio_irq_restore()
2618 pctrl->hwirq[i]); in rzg2l_gpio_irq_restore()
2624 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); in rzg2l_gpio_irq_restore()
2632 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_restore()
2636 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_restore()
2639 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); in rzg2l_gpio_irq_restore()
2651 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); in rzg2l_gpio_irq_domain_free() local
2657 if (pctrl->hwirq[i] == hwirq) { in rzg2l_gpio_irq_domain_free()
2658 rzg2l_gpio_irq_endisable(pctrl, hwirq, false); in rzg2l_gpio_irq_domain_free()
2660 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
2661 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); in rzg2l_gpio_irq_domain_free()
2662 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
2663 pctrl->hwirq[i] = 0; in rzg2l_gpio_irq_domain_free()
2675 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); in rzg2l_init_irq_valid_mask() local
2676 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_init_irq_valid_mask()
2686 if (port >= pctrl->data->n_ports || in rzg2l_init_irq_valid_mask()
2688 pctrl->data->port_pin_configs[port]))) in rzg2l_init_irq_valid_mask()
2693 static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) in rzg2l_pinctrl_reg_cache_alloc() argument
2695 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_reg_cache_alloc()
2698 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2702 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2706 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2710 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2714 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2718 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2723 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_reg_cache_alloc()
2725 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), in rzg2l_pinctrl_reg_cache_alloc()
2730 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), in rzg2l_pinctrl_reg_cache_alloc()
2735 cache->pupd[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pupd[i]), in rzg2l_pinctrl_reg_cache_alloc()
2741 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, in rzg2l_pinctrl_reg_cache_alloc()
2747 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, in rzg2l_pinctrl_reg_cache_alloc()
2754 pctrl->cache = cache; in rzg2l_pinctrl_reg_cache_alloc()
2755 pctrl->dedicated_cache = dedicated_cache; in rzg2l_pinctrl_reg_cache_alloc()
2760 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) in rzg2l_gpio_register() argument
2762 struct device_node *np = pctrl->dev->of_node; in rzg2l_gpio_register()
2763 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_gpio_register()
2764 const char *name = dev_name(pctrl->dev); in rzg2l_gpio_register()
2782 return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n"); in rzg2l_gpio_register()
2787 of_args.args[2] != pctrl->data->n_port_pins) in rzg2l_gpio_register()
2788 return dev_err_probe(pctrl->dev, -EINVAL, in rzg2l_gpio_register()
2791 chip->names = pctrl->data->port_pins; in rzg2l_gpio_register()
2800 chip->parent = pctrl->dev; in rzg2l_gpio_register()
2807 girq->fwnode = dev_fwnode(pctrl->dev); in rzg2l_gpio_register()
2814 pctrl->gpio_range.id = 0; in rzg2l_gpio_register()
2815 pctrl->gpio_range.pin_base = 0; in rzg2l_gpio_register()
2816 pctrl->gpio_range.base = 0; in rzg2l_gpio_register()
2817 pctrl->gpio_range.npins = chip->ngpio; in rzg2l_gpio_register()
2818 pctrl->gpio_range.name = chip->label; in rzg2l_gpio_register()
2819 pctrl->gpio_range.gc = chip; in rzg2l_gpio_register()
2820 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); in rzg2l_gpio_register()
2822 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n"); in rzg2l_gpio_register()
2824 dev_dbg(pctrl->dev, "Registered gpio controller\n"); in rzg2l_gpio_register()
2829 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) in rzg2l_pinctrl_register() argument
2831 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_register()
2837 pctrl->desc.name = DRV_NAME; in rzg2l_pinctrl_register()
2838 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_register()
2839 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; in rzg2l_pinctrl_register()
2840 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; in rzg2l_pinctrl_register()
2841 pctrl->desc.confops = &rzg2l_pinctrl_confops; in rzg2l_pinctrl_register()
2842 pctrl->desc.owner = THIS_MODULE; in rzg2l_pinctrl_register()
2843 if (pctrl->data->num_custom_params) { in rzg2l_pinctrl_register()
2844 pctrl->desc.num_custom_params = pctrl->data->num_custom_params; in rzg2l_pinctrl_register()
2845 pctrl->desc.custom_params = pctrl->data->custom_params; in rzg2l_pinctrl_register()
2847 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items; in rzg2l_pinctrl_register()
2851 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); in rzg2l_pinctrl_register()
2855 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, in rzg2l_pinctrl_register()
2860 pctrl->pins = pins; in rzg2l_pinctrl_register()
2861 pctrl->desc.pins = pins; in rzg2l_pinctrl_register()
2863 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { in rzg2l_pinctrl_register()
2865 pins[i].name = pctrl->data->port_pins[i]; in rzg2l_pinctrl_register()
2868 pin_data[i] = pctrl->data->port_pin_configs[j]; in rzg2l_pinctrl_register()
2870 pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, in rzg2l_pinctrl_register()
2877 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_register()
2878 unsigned int index = pctrl->data->n_port_pins + i; in rzg2l_pinctrl_register()
2881 pins[index].name = pctrl->data->dedicated_pins[i].name; in rzg2l_pinctrl_register()
2882 pin_data[index] = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_register()
2886 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), in rzg2l_pinctrl_register()
2888 if (!pctrl->settings) in rzg2l_pinctrl_register()
2891 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { in rzg2l_pinctrl_register()
2893 pctrl->settings[i].power_source = 3300; in rzg2l_pinctrl_register()
2895 ret = rzg2l_get_power_source(pctrl, i, pin_data[i]); in rzg2l_pinctrl_register()
2898 pctrl->settings[i].power_source = ret; in rzg2l_pinctrl_register()
2902 ret = rzg2l_pinctrl_reg_cache_alloc(pctrl); in rzg2l_pinctrl_register()
2906 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, in rzg2l_pinctrl_register()
2907 &pctrl->pctl); in rzg2l_pinctrl_register()
2909 return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n"); in rzg2l_pinctrl_register()
2911 ret = pinctrl_enable(pctrl->pctl); in rzg2l_pinctrl_register()
2913 return dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n"); in rzg2l_pinctrl_register()
2915 ret = rzg2l_gpio_register(pctrl); in rzg2l_pinctrl_register()
2917 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n"); in rzg2l_pinctrl_register()
2924 struct rzg2l_pinctrl *pctrl; in rzg2l_pinctrl_probe() local
2942 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in rzg2l_pinctrl_probe()
2943 if (!pctrl) in rzg2l_pinctrl_probe()
2946 pctrl->dev = &pdev->dev; in rzg2l_pinctrl_probe()
2948 pctrl->data = of_device_get_match_data(&pdev->dev); in rzg2l_pinctrl_probe()
2949 if (!pctrl->data) in rzg2l_pinctrl_probe()
2952 pctrl->base = devm_platform_ioremap_resource(pdev, 0); in rzg2l_pinctrl_probe()
2953 if (IS_ERR(pctrl->base)) in rzg2l_pinctrl_probe()
2954 return PTR_ERR(pctrl->base); in rzg2l_pinctrl_probe()
2956 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); in rzg2l_pinctrl_probe()
2957 if (IS_ERR(pctrl->clk)) { in rzg2l_pinctrl_probe()
2958 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), in rzg2l_pinctrl_probe()
2962 spin_lock_init(&pctrl->lock); in rzg2l_pinctrl_probe()
2963 spin_lock_init(&pctrl->bitmap_lock); in rzg2l_pinctrl_probe()
2964 mutex_init(&pctrl->mutex); in rzg2l_pinctrl_probe()
2965 atomic_set(&pctrl->wakeup_path, 0); in rzg2l_pinctrl_probe()
2967 platform_set_drvdata(pdev, pctrl); in rzg2l_pinctrl_probe()
2969 ret = rzg2l_pinctrl_register(pctrl); in rzg2l_pinctrl_probe()
2973 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); in rzg2l_pinctrl_probe()
2977 static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend) in rzg2l_pinctrl_pm_setup_regs() argument
2979 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_pm_setup_regs()
2980 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_pm_setup_regs()
2988 cfg = pctrl->data->port_pin_configs[port]; in rzg2l_pinctrl_pm_setup_regs()
2998 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); in rzg2l_pinctrl_pm_setup_regs()
3004 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); in rzg2l_pinctrl_pm_setup_regs()
3006 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), in rzg2l_pinctrl_pm_setup_regs()
3009 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, in rzg2l_pinctrl_pm_setup_regs()
3015 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), in rzg2l_pinctrl_pm_setup_regs()
3018 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), in rzg2l_pinctrl_pm_setup_regs()
3023 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); in rzg2l_pinctrl_pm_setup_regs()
3024 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); in rzg2l_pinctrl_pm_setup_regs()
3027 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), in rzg2l_pinctrl_pm_setup_regs()
3030 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, in rzg2l_pinctrl_pm_setup_regs()
3037 static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) in rzg2l_pinctrl_pm_setup_dedicated_regs() argument
3039 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; in rzg2l_pinctrl_pm_setup_dedicated_regs()
3047 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_pm_setup_dedicated_regs()
3053 cfg = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_pm_setup_dedicated_regs()
3055 if (i + 1 < pctrl->data->n_dedicated_pins) { in rzg2l_pinctrl_pm_setup_dedicated_regs()
3056 next_cfg = pctrl->data->dedicated_pins[i + 1].config; in rzg2l_pinctrl_pm_setup_dedicated_regs()
3072 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), in rzg2l_pinctrl_pm_setup_dedicated_regs()
3076 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), in rzg2l_pinctrl_pm_setup_dedicated_regs()
3083 pctrl->base + IOLH(off) + 4, in rzg2l_pinctrl_pm_setup_dedicated_regs()
3088 pctrl->base + IEN(off) + 4, in rzg2l_pinctrl_pm_setup_dedicated_regs()
3096 static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) in rzg2l_pinctrl_pm_setup_pfc() argument
3098 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_pm_setup_pfc()
3101 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_pm_setup_pfc()
3102 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); in rzg2l_pinctrl_pm_setup_pfc()
3113 cfg = pctrl->data->port_pin_configs[port]; in rzg2l_pinctrl_pm_setup_pfc()
3118 pm = readw(pctrl->base + PM(off)); in rzg2l_pinctrl_pm_setup_pfc()
3120 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_pm_setup_pfc()
3128 writew(pm, pctrl->base + PM(off)); in rzg2l_pinctrl_pm_setup_pfc()
3132 writeb(pmc, pctrl->base + PMC(off)); in rzg2l_pinctrl_pm_setup_pfc()
3137 writel(pfc, pctrl->base + PFC(off)); in rzg2l_pinctrl_pm_setup_pfc()
3141 writeb(pmc, pctrl->base + PMC(off)); in rzg2l_pinctrl_pm_setup_pfc()
3145 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); in rzg2l_pinctrl_pm_setup_pfc()
3146 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_pm_setup_pfc()
3151 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); in rzg2l_pinctrl_suspend_noirq() local
3152 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_suspend_noirq()
3154 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_suspend_noirq()
3156 rzg2l_pinctrl_pm_setup_regs(pctrl, true); in rzg2l_pinctrl_suspend_noirq()
3157 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); in rzg2l_pinctrl_suspend_noirq()
3161 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); in rzg2l_pinctrl_suspend_noirq()
3163 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); in rzg2l_pinctrl_suspend_noirq()
3166 cache->qspi = readb(pctrl->base + QSPI); in rzg2l_pinctrl_suspend_noirq()
3167 cache->eth_mode = readb(pctrl->base + ETH_MODE); in rzg2l_pinctrl_suspend_noirq()
3169 if (!atomic_read(&pctrl->wakeup_path)) in rzg2l_pinctrl_suspend_noirq()
3170 clk_disable_unprepare(pctrl->clk); in rzg2l_pinctrl_suspend_noirq()
3179 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); in rzg2l_pinctrl_resume_noirq() local
3180 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_resume_noirq()
3182 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_resume_noirq()
3185 if (!atomic_read(&pctrl->wakeup_path)) { in rzg2l_pinctrl_resume_noirq()
3186 ret = clk_prepare_enable(pctrl->clk); in rzg2l_pinctrl_resume_noirq()
3191 writeb(cache->qspi, pctrl->base + QSPI); in rzg2l_pinctrl_resume_noirq()
3192 writeb(cache->eth_mode, pctrl->base + ETH_MODE); in rzg2l_pinctrl_resume_noirq()
3195 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); in rzg2l_pinctrl_resume_noirq()
3197 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); in rzg2l_pinctrl_resume_noirq()
3200 rzg2l_pinctrl_pm_setup_pfc(pctrl); in rzg2l_pinctrl_resume_noirq()
3201 rzg2l_pinctrl_pm_setup_regs(pctrl, false); in rzg2l_pinctrl_resume_noirq()
3202 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); in rzg2l_pinctrl_resume_noirq()
3203 rzg2l_gpio_irq_restore(pctrl); in rzg2l_pinctrl_resume_noirq()
3208 static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) in rzg2l_pwpr_pfc_lock_unlock() argument
3210 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzg2l_pwpr_pfc_lock_unlock()
3214 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3215 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3218 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3219 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ in rzg2l_pwpr_pfc_lock_unlock()
3223 static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) in rzv2h_pwpr_pfc_lock_unlock() argument
3225 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzv2h_pwpr_pfc_lock_unlock()
3230 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3231 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3234 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3235 writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()