Lines Matching refs:pctl
303 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_request() local
307 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); in stm32_gpio_request()
309 dev_err(pctl->dev, "pin %d not in range.\n", pin); in stm32_gpio_request()
315 dev_err(pctl->dev, "pin %d not available.\n", pin); in stm32_gpio_request()
397 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_init_valid_mask() local
411 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i); in stm32_gpio_init_valid_mask()
424 dev_dbg(pctl->dev, "RIF semaphore ownership conflict, GPIO %u", i); in stm32_gpio_init_valid_mask()
496 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_irq_request_resources() local
505 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", in stm32_gpio_irq_request_resources()
557 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_activate() local
560 if (pctl->hwlock) { in stm32_gpio_domain_activate()
561 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_gpio_domain_activate()
564 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_gpio_domain_activate()
569 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); in stm32_gpio_domain_activate()
571 if (pctl->hwlock) in stm32_gpio_domain_activate()
572 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_gpio_domain_activate()
584 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_alloc() local
593 spin_lock_irqsave(&pctl->irqmux_lock, flags); in stm32_gpio_domain_alloc()
595 if (pctl->irqmux_map & BIT(hwirq)) { in stm32_gpio_domain_alloc()
596 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq); in stm32_gpio_domain_alloc()
599 pctl->irqmux_map |= BIT(hwirq); in stm32_gpio_domain_alloc()
602 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); in stm32_gpio_domain_alloc()
621 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_free() local
627 spin_lock_irqsave(&pctl->irqmux_lock, flags); in stm32_gpio_domain_free()
628 pctl->irqmux_map &= ~BIT(hwirq); in stm32_gpio_domain_free()
629 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); in stm32_gpio_domain_free()
641 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) in stm32_pctrl_find_group_by_pin() argument
645 for (i = 0; i < pctl->ngroups; i++) { in stm32_pctrl_find_group_by_pin()
646 struct stm32_pinctrl_group *grp = pctl->groups + i; in stm32_pctrl_find_group_by_pin()
655 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, in stm32_pctrl_is_function_valid() argument
660 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_is_function_valid()
661 const struct stm32_desc_pin *pin = pctl->pins + i; in stm32_pctrl_is_function_valid()
679 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num); in stm32_pctrl_is_function_valid()
684 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, in stm32_pctrl_dt_node_to_map_func() argument
695 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) in stm32_pctrl_dt_node_to_map_func()
710 struct stm32_pinctrl *pctl; in stm32_pctrl_dt_subnode_to_map() local
720 pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_dt_subnode_to_map()
724 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", in stm32_pctrl_dt_subnode_to_map()
766 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { in stm32_pctrl_dt_subnode_to_map()
771 grp = stm32_pctrl_find_group_by_pin(pctl, pin); in stm32_pctrl_dt_subnode_to_map()
773 dev_err(pctl->dev, "unable to match pin %d to group\n", in stm32_pctrl_dt_subnode_to_map()
779 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, in stm32_pctrl_dt_subnode_to_map()
824 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_get_groups_count() local
826 return pctl->ngroups; in stm32_pctrl_get_groups_count()
832 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_get_group_name() local
834 return pctl->groups[group].name; in stm32_pctrl_get_group_name()
842 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_get_group_pins() local
844 *pins = (unsigned *)&pctl->groups[group].pin; in stm32_pctrl_get_group_pins()
877 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pmx_get_func_groups() local
879 *groups = pctl->grp_names; in stm32_pmx_get_func_groups()
880 *num_groups = pctl->ngroups; in stm32_pmx_get_func_groups()
888 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pmx_set_mode() local
897 if (pctl->hwlock) { in stm32_pmx_set_mode()
898 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pmx_set_mode()
901 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pmx_set_mode()
916 if (pctl->hwlock) in stm32_pmx_set_mode()
917 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pmx_set_mode()
952 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pmx_set_mux() local
953 struct stm32_pinctrl_group *g = pctl->groups + group; in stm32_pmx_set_mux()
959 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); in stm32_pmx_set_mux()
965 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pmx_set_mux()
970 dev_dbg(pctl->dev, "Reserved pins, skipping HW update.\n"); in stm32_pmx_set_mux()
995 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pmx_request() local
1000 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pmx_request()
1005 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio); in stm32_pmx_request()
1027 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_driving() local
1034 if (pctl->hwlock) { in stm32_pconf_set_driving()
1035 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_driving()
1038 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_driving()
1048 if (pctl->hwlock) in stm32_pconf_set_driving()
1049 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_driving()
1078 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_speed() local
1085 if (pctl->hwlock) { in stm32_pconf_set_speed()
1086 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_speed()
1089 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_speed()
1099 if (pctl->hwlock) in stm32_pconf_set_speed()
1100 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_speed()
1129 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_bias() local
1136 if (pctl->hwlock) { in stm32_pconf_set_bias()
1137 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_bias()
1140 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_bias()
1150 if (pctl->hwlock) in stm32_pconf_set_bias()
1151 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_bias()
1201 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_parse_conf() local
1208 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pconf_parse_conf()
1216 dev_warn(pctl->dev, "Can't access gpio %d\n", pin); in stm32_pconf_parse_conf()
1254 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_group_get() local
1256 *config = pctl->groups[group].config; in stm32_pconf_group_get()
1264 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_group_set() local
1265 struct stm32_pinctrl_group *g = &pctl->groups[group]; in stm32_pconf_group_set()
1300 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl, in stm32_pconf_get_pin_desc_by_pin_number() argument
1303 struct stm32_desc_pin *pins = pctl->pins; in stm32_pconf_get_pin_desc_by_pin_number()
1306 for (i = 0; i < pctl->npins; i++) { in stm32_pconf_get_pin_desc_by_pin_number()
1318 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_dbg_show() local
1374 pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin); in stm32_pconf_dbg_show()
1398 static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl, in stm32_pctrl_get_desc_pin_from_gpio() argument
1407 if (stm32_pin_nb < pctl->npins) { in stm32_pctrl_get_desc_pin_from_gpio()
1408 pin_desc = pctl->pins + stm32_pin_nb; in stm32_pctrl_get_desc_pin_from_gpio()
1414 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_get_desc_pin_from_gpio()
1415 pin_desc = pctl->pins + i; in stm32_pctrl_get_desc_pin_from_gpio()
1422 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode) in stm32_gpiolib_register_bank() argument
1424 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; in stm32_gpiolib_register_bank()
1428 struct device *dev = pctl->dev; in stm32_gpiolib_register_bank()
1458 bank_nr = pctl->nbanks; in stm32_gpiolib_register_bank()
1466 pinctrl_add_gpio_range(pctl->pctl_dev, in stm32_gpiolib_register_bank()
1467 &pctl->banks[bank_nr].range); in stm32_gpiolib_register_bank()
1480 bank->secure_control = pctl->match_data->secure_control; in stm32_gpiolib_register_bank()
1481 bank->rif_control = pctl->match_data->rif_control; in stm32_gpiolib_register_bank()
1484 if (pctl->domain) { in stm32_gpiolib_register_bank()
1488 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, in stm32_gpiolib_register_bank()
1501 stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i); in stm32_gpiolib_register_bank()
1546 struct stm32_pinctrl *pctl) in stm32_pctrl_dt_setup_irq() argument
1554 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in stm32_pctrl_dt_setup_irq()
1555 if (IS_ERR(pctl->regmap)) in stm32_pctrl_dt_setup_irq()
1556 return PTR_ERR(pctl->regmap); in stm32_pctrl_dt_setup_irq()
1558 rm = pctl->regmap; in stm32_pctrl_dt_setup_irq()
1580 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); in stm32_pctrl_dt_setup_irq()
1581 if (IS_ERR(pctl->irqmux[i])) in stm32_pctrl_dt_setup_irq()
1582 return PTR_ERR(pctl->irqmux[i]); in stm32_pctrl_dt_setup_irq()
1590 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); in stm32_pctrl_build_state() local
1593 pctl->ngroups = pctl->npins; in stm32_pctrl_build_state()
1596 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1597 sizeof(*pctl->groups), GFP_KERNEL); in stm32_pctrl_build_state()
1598 if (!pctl->groups) in stm32_pctrl_build_state()
1602 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1603 sizeof(*pctl->grp_names), GFP_KERNEL); in stm32_pctrl_build_state()
1604 if (!pctl->grp_names) in stm32_pctrl_build_state()
1607 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_build_state()
1608 const struct stm32_desc_pin *pin = pctl->pins + i; in stm32_pctrl_build_state()
1609 struct stm32_pinctrl_group *group = pctl->groups + i; in stm32_pctrl_build_state()
1613 pctl->grp_names[i] = pin->pin.name; in stm32_pctrl_build_state()
1619 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl, in stm32_pctrl_create_pins_tab() argument
1625 for (i = 0; i < pctl->match_data->npins; i++) { in stm32_pctrl_create_pins_tab()
1626 p = pctl->match_data->pins + i; in stm32_pctrl_create_pins_tab()
1627 if (pctl->pkg && !(pctl->pkg & p->pkg)) in stm32_pctrl_create_pins_tab()
1636 pctl->npins = nb_pins_available; in stm32_pctrl_create_pins_tab()
1646 struct stm32_pinctrl *pctl; in stm32_pctl_probe() local
1655 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); in stm32_pctl_probe()
1656 if (!pctl) in stm32_pctl_probe()
1659 platform_set_drvdata(pdev, pctl); in stm32_pctl_probe()
1662 pctl->domain = stm32_pctrl_get_irq_domain(pdev); in stm32_pctl_probe()
1663 if (IS_ERR(pctl->domain)) in stm32_pctl_probe()
1664 return PTR_ERR(pctl->domain); in stm32_pctl_probe()
1665 if (!pctl->domain) in stm32_pctl_probe()
1674 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); in stm32_pctl_probe()
1677 spin_lock_init(&pctl->irqmux_lock); in stm32_pctl_probe()
1679 pctl->dev = dev; in stm32_pctl_probe()
1680 pctl->match_data = match_data; in stm32_pctl_probe()
1683 if (!device_property_read_u32(dev, "st,package", &pctl->pkg)) in stm32_pctl_probe()
1684 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); in stm32_pctl_probe()
1686 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, in stm32_pctl_probe()
1687 sizeof(*pctl->pins), GFP_KERNEL); in stm32_pctl_probe()
1688 if (!pctl->pins) in stm32_pctl_probe()
1691 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); in stm32_pctl_probe()
1701 if (pctl->domain) { in stm32_pctl_probe()
1702 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); in stm32_pctl_probe()
1707 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), in stm32_pctl_probe()
1712 for (i = 0; i < pctl->npins; i++) in stm32_pctl_probe()
1713 pins[i] = pctl->pins[i].pin; in stm32_pctl_probe()
1715 pctl->pctl_desc.name = dev_name(&pdev->dev); in stm32_pctl_probe()
1716 pctl->pctl_desc.owner = THIS_MODULE; in stm32_pctl_probe()
1717 pctl->pctl_desc.pins = pins; in stm32_pctl_probe()
1718 pctl->pctl_desc.npins = pctl->npins; in stm32_pctl_probe()
1719 pctl->pctl_desc.link_consumers = true; in stm32_pctl_probe()
1720 pctl->pctl_desc.confops = &stm32_pconf_ops; in stm32_pctl_probe()
1721 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; in stm32_pctl_probe()
1722 pctl->pctl_desc.pmxops = &stm32_pmx_ops; in stm32_pctl_probe()
1723 pctl->dev = &pdev->dev; in stm32_pctl_probe()
1725 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, in stm32_pctl_probe()
1726 pctl); in stm32_pctl_probe()
1728 if (IS_ERR(pctl->pctl_dev)) { in stm32_pctl_probe()
1730 return PTR_ERR(pctl->pctl_dev); in stm32_pctl_probe()
1738 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), in stm32_pctl_probe()
1740 if (!pctl->banks) in stm32_pctl_probe()
1743 pctl->clks = devm_kcalloc(dev, banks, sizeof(*pctl->clks), in stm32_pctl_probe()
1745 if (!pctl->clks) in stm32_pctl_probe()
1750 struct stm32_gpio_bank *bank = &pctl->banks[i]; in stm32_pctl_probe()
1759 pctl->clks[i].clk = of_clk_get_by_name(np, NULL); in stm32_pctl_probe()
1760 if (IS_ERR(pctl->clks[i].clk)) { in stm32_pctl_probe()
1762 return dev_err_probe(dev, PTR_ERR(pctl->clks[i].clk), in stm32_pctl_probe()
1765 pctl->clks[i].id = "pctl"; in stm32_pctl_probe()
1769 ret = clk_bulk_prepare_enable(banks, pctl->clks); in stm32_pctl_probe()
1776 ret = stm32_gpiolib_register_bank(pctl, child); in stm32_pctl_probe()
1782 pctl->nbanks++; in stm32_pctl_probe()
1789 for (i = 0; i < pctl->nbanks; i++) { in stm32_pctl_probe()
1790 struct stm32_gpio_bank *bank = &pctl->banks[i]; in stm32_pctl_probe()
1795 clk_bulk_disable_unprepare(banks, pctl->clks); in stm32_pctl_probe()
1801 struct stm32_pinctrl *pctl, u32 pin) in stm32_pinctrl_restore_gpio_regs() argument
1803 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); in stm32_pinctrl_restore_gpio_regs()
1810 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); in stm32_pinctrl_restore_gpio_regs()
1858 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); in stm32_pinctrl_restore_gpio_regs()
1865 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); in stm32_pinctrl_suspend() local
1867 clk_bulk_disable(pctl->nbanks, pctl->clks); in stm32_pinctrl_suspend()
1875 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); in stm32_pinctrl_resume() local
1876 struct stm32_pinctrl_group *g = pctl->groups; in stm32_pinctrl_resume()
1879 ret = clk_bulk_enable(pctl->nbanks, pctl->clks); in stm32_pinctrl_resume()
1883 for (i = 0; i < pctl->ngroups; i++, g++) in stm32_pinctrl_resume()
1884 stm32_pinctrl_restore_gpio_regs(pctl, g->pin); in stm32_pinctrl_resume()