Lines Matching refs:pwr_ctrl
115 struct power_table_control *pwr_ctrl = &config_store.mode_set[idx].power_control; in amd_pmf_set_automode() local
117 amd_pmf_send_cmd(dev, SET_SPL, false, pwr_ctrl->spl, NULL); in amd_pmf_set_automode()
118 amd_pmf_send_cmd(dev, SET_FPPT, false, pwr_ctrl->fppt, NULL); in amd_pmf_set_automode()
119 amd_pmf_send_cmd(dev, SET_SPPT, false, pwr_ctrl->sppt, NULL); in amd_pmf_set_automode()
120 amd_pmf_send_cmd(dev, SET_SPPT_APU_ONLY, false, pwr_ctrl->sppt_apu_only, NULL); in amd_pmf_set_automode()
121 amd_pmf_send_cmd(dev, SET_STT_MIN_LIMIT, false, pwr_ctrl->stt_min, NULL); in amd_pmf_set_automode()
123 fixp_q88_fromint(pwr_ctrl->stt_skin_temp[STT_TEMP_APU]), NULL); in amd_pmf_set_automode()
125 fixp_q88_fromint(pwr_ctrl->stt_skin_temp[STT_TEMP_HS2]), NULL); in amd_pmf_set_automode()
305 struct power_table_control *pwr_ctrl; in amd_pmf_load_defaults_auto_mode() local
339 pwr_ctrl = &config_store.mode_set[AUTO_QUIET].power_control; in amd_pmf_load_defaults_auto_mode()
340 pwr_ctrl->spl = output.spl_quiet; in amd_pmf_load_defaults_auto_mode()
341 pwr_ctrl->sppt = output.sppt_quiet; in amd_pmf_load_defaults_auto_mode()
342 pwr_ctrl->fppt = output.fppt_quiet; in amd_pmf_load_defaults_auto_mode()
343 pwr_ctrl->sppt_apu_only = output.sppt_apu_only_quiet; in amd_pmf_load_defaults_auto_mode()
344 pwr_ctrl->stt_min = output.stt_min_limit_quiet; in amd_pmf_load_defaults_auto_mode()
345 pwr_ctrl->stt_skin_temp[STT_TEMP_APU] = output.stt_apu_quiet; in amd_pmf_load_defaults_auto_mode()
346 pwr_ctrl->stt_skin_temp[STT_TEMP_HS2] = output.stt_hs2_quiet; in amd_pmf_load_defaults_auto_mode()
348 pwr_ctrl = &config_store.mode_set[AUTO_BALANCE].power_control; in amd_pmf_load_defaults_auto_mode()
349 pwr_ctrl->spl = output.spl_balanced; in amd_pmf_load_defaults_auto_mode()
350 pwr_ctrl->sppt = output.sppt_balanced; in amd_pmf_load_defaults_auto_mode()
351 pwr_ctrl->fppt = output.fppt_balanced; in amd_pmf_load_defaults_auto_mode()
352 pwr_ctrl->sppt_apu_only = output.sppt_apu_only_balanced; in amd_pmf_load_defaults_auto_mode()
353 pwr_ctrl->stt_min = output.stt_min_limit_balanced; in amd_pmf_load_defaults_auto_mode()
354 pwr_ctrl->stt_skin_temp[STT_TEMP_APU] = output.stt_apu_balanced; in amd_pmf_load_defaults_auto_mode()
355 pwr_ctrl->stt_skin_temp[STT_TEMP_HS2] = output.stt_hs2_balanced; in amd_pmf_load_defaults_auto_mode()
357 pwr_ctrl = &config_store.mode_set[AUTO_PERFORMANCE].power_control; in amd_pmf_load_defaults_auto_mode()
358 pwr_ctrl->spl = output.spl_perf; in amd_pmf_load_defaults_auto_mode()
359 pwr_ctrl->sppt = output.sppt_perf; in amd_pmf_load_defaults_auto_mode()
360 pwr_ctrl->fppt = output.fppt_perf; in amd_pmf_load_defaults_auto_mode()
361 pwr_ctrl->sppt_apu_only = output.sppt_apu_only_perf; in amd_pmf_load_defaults_auto_mode()
362 pwr_ctrl->stt_min = output.stt_min_limit_perf; in amd_pmf_load_defaults_auto_mode()
363 pwr_ctrl->stt_skin_temp[STT_TEMP_APU] = output.stt_apu_perf; in amd_pmf_load_defaults_auto_mode()
364 pwr_ctrl->stt_skin_temp[STT_TEMP_HS2] = output.stt_hs2_perf; in amd_pmf_load_defaults_auto_mode()
366 pwr_ctrl = &config_store.mode_set[AUTO_PERFORMANCE_ON_LAP].power_control; in amd_pmf_load_defaults_auto_mode()
367 pwr_ctrl->spl = output.spl_perf_on_lap; in amd_pmf_load_defaults_auto_mode()
368 pwr_ctrl->sppt = output.sppt_perf_on_lap; in amd_pmf_load_defaults_auto_mode()
369 pwr_ctrl->fppt = output.fppt_perf_on_lap; in amd_pmf_load_defaults_auto_mode()
370 pwr_ctrl->sppt_apu_only = output.sppt_apu_only_perf_on_lap; in amd_pmf_load_defaults_auto_mode()
371 pwr_ctrl->stt_min = output.stt_min_limit_perf_on_lap; in amd_pmf_load_defaults_auto_mode()
372 pwr_ctrl->stt_skin_temp[STT_TEMP_APU] = output.stt_apu_perf_on_lap; in amd_pmf_load_defaults_auto_mode()
373 pwr_ctrl->stt_skin_temp[STT_TEMP_HS2] = output.stt_hs2_perf_on_lap; in amd_pmf_load_defaults_auto_mode()