Lines Matching refs:control
128 u32 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_disable() local
130 control &= ~CONTROL_ENABLE; in mchp_corespi_disable()
132 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_disable()
163 u32 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_enable_ints() local
165 control |= INT_ENABLE_MASK; in mchp_corespi_enable_ints()
166 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_enable_ints()
171 u32 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_disable_ints() local
173 control &= ~INT_ENABLE_MASK; in mchp_corespi_disable_ints()
174 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_disable_ints()
179 u32 control; in mchp_corespi_set_xfer_size() local
211 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_set_xfer_size()
212 control &= ~CONTROL_FRAMECNT_MASK; in mchp_corespi_set_xfer_size()
213 control |= lenpart << CONTROL_FRAMECNT_SHIFT; in mchp_corespi_set_xfer_size()
214 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_xfer_size()
246 u32 control; in mchp_corespi_set_framesize() local
255 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_set_framesize()
256 control &= ~CONTROL_ENABLE; in mchp_corespi_set_framesize()
257 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_framesize()
261 control |= CONTROL_ENABLE; in mchp_corespi_set_framesize()
262 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_framesize()
312 u32 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_init() local
314 control &= ~CONTROL_ENABLE; in mchp_corespi_init()
315 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_init()
317 control |= CONTROL_MASTER; in mchp_corespi_init()
318 control &= ~CONTROL_MODE_MASK; in mchp_corespi_init()
319 control |= MOTOROLA_MODE; in mchp_corespi_init()
329 control |= CONTROL_SPS | CONTROL_BIGFIFO; in mchp_corespi_init()
331 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_init()
349 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_init()
351 control &= ~CONTROL_RESET; in mchp_corespi_init()
352 control |= CONTROL_ENABLE; in mchp_corespi_init()
354 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_init()
359 u32 control; in mchp_corespi_set_clk_gen() local
361 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_set_clk_gen()
363 control |= CONTROL_CLKMODE; in mchp_corespi_set_clk_gen()
365 control &= ~CONTROL_CLKMODE; in mchp_corespi_set_clk_gen()
368 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_clk_gen()
374 u32 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_set_mode() local
396 control &= ~CONTROL_ENABLE; in mchp_corespi_set_mode()
397 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_mode()
399 control &= ~(SPI_MODE_X_MASK << MODE_X_MASK_SHIFT); in mchp_corespi_set_mode()
400 control |= mode_val; in mchp_corespi_set_mode()
402 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_mode()
404 control |= CONTROL_ENABLE; in mchp_corespi_set_mode()
405 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_set_mode()