Lines Matching refs:low
184 u32 low, high; in intel_tcc_get_tjmax() local
188 err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); in intel_tcc_get_tjmax()
190 err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); in intel_tcc_get_tjmax()
194 val = (low >> 16) & 0xff; in intel_tcc_get_tjmax()
211 u32 low, high; in intel_tcc_get_offset() local
215 err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); in intel_tcc_get_offset()
217 err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); in intel_tcc_get_offset()
221 return (low >> 24) & intel_tcc_temp_masks.tcc_offset; in intel_tcc_get_offset()
238 u32 low, high; in intel_tcc_set_offset() local
248 err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); in intel_tcc_set_offset()
250 err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); in intel_tcc_set_offset()
255 if (low & BIT(31)) in intel_tcc_set_offset()
258 low &= ~(intel_tcc_temp_masks.tcc_offset << 24); in intel_tcc_set_offset()
259 low |= offset << 24; in intel_tcc_set_offset()
262 return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, low, high); in intel_tcc_set_offset()
264 return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, low, high); in intel_tcc_set_offset()
282 u32 low, high, mask; in intel_tcc_get_temp() local
290 err = rdmsr_safe(msr, &low, &high); in intel_tcc_get_temp()
292 err = rdmsr_safe_on_cpu(cpu, msr, &low, &high); in intel_tcc_get_temp()
297 if (!(low & BIT(31))) in intel_tcc_get_temp()
302 *temp = tjmax - ((low >> 16) & mask); in intel_tcc_get_temp()