Lines Matching refs:TB_CFG_SWITCH
1590 TB_CFG_SWITCH, 2, 2); in tb_switch_reset_host()
1618 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_3, 1); in tb_switch_enumerated()
1685 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1); in tb_switch_wait_for_bit()
1714 res = tb_sw_write(sw, ((u32 *) &sw->config) + 4, TB_CFG_SWITCH, 4, 1); in tb_plug_events_active()
1718 res = tb_sw_read(sw, &data, TB_CFG_SWITCH, sw->cap_plug_events + 1, 1); in tb_plug_events_active()
1741 return tb_sw_write(sw, &data, TB_CFG_SWITCH, in tb_plug_events_active()
2439 ret = tb_cfg_read(tb->ctl, &sw->config, route, 0, TB_CFG_SWITCH, 0, 5); in tb_switch_alloc()
2595 ret = tb_sw_write(sw, (u32 *)&sw->config + 1, TB_CFG_SWITCH, in tb_switch_configure()
2612 ret = tb_sw_write(sw, (u32 *)&sw->config + 1, TB_CFG_SWITCH, in tb_switch_configure()
3822 ret = tb_sw_write(sw, &value, TB_CFG_SWITCH, offset, 1); in tb_switch_pcie_bridge_write()
3835 ret = tb_sw_write(sw, &command, TB_CFG_SWITCH, offset, 1); in tb_switch_pcie_bridge_write()
3844 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1); in tb_switch_pcie_bridge_write()