Lines Matching refs:d2
1068 unsigned int d1, d2; in mvebu_uart_clock_prepare() local
1101 d2 = uart_clock_base->div / CLK_TBG_DIV1_MAX; in mvebu_uart_clock_prepare()
1104 d2 = 1; in mvebu_uart_clock_prepare()
1123 prev_clock_rate * d1 * d2); in mvebu_uart_clock_prepare()
1137 val |= d2 << CLK_TBG_DIV2_SHIFT; in mvebu_uart_clock_prepare()
1152 prev_clock_rate * d1 * d2); in mvebu_uart_clock_prepare()
1332 unsigned int d1, d2; in mvebu_uart_clock_probe() local
1429 d2 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR * in mvebu_uart_clock_probe()
1431 if (d2 < 1) in mvebu_uart_clock_probe()
1432 d2 = 1; in mvebu_uart_clock_probe()
1433 else if (d2 > CLK_TBG_DIV2_MAX) in mvebu_uart_clock_probe()
1434 d2 = CLK_TBG_DIV2_MAX; in mvebu_uart_clock_probe()
1440 d1 = d2 = 1; in mvebu_uart_clock_probe()
1444 if (rate > 9600 * OSAMP_MAX_DIVISOR * BRDV_BAUD_MAX * d1 * d2) in mvebu_uart_clock_probe()
1453 (i != PARENT_CLOCK_XTAL && div > d1 * d2)) { in mvebu_uart_clock_probe()
1455 div = d1 * d2; in mvebu_uart_clock_probe()