Lines Matching refs:minfo
38 static void DAC1064_calcclock(const struct matrox_fb_info *minfo, in DAC1064_calcclock() argument
50 fvco = PLL_calcclock(minfo, freq, fmax, in, feed, &p); in DAC1064_calcclock()
89 static void DAC1064_setpclk(struct matrox_fb_info *minfo, unsigned long fout) in DAC1064_setpclk() argument
95 DAC1064_calcclock(minfo, fout, minfo->max_pixel_clock, &m, &n, &p); in DAC1064_setpclk()
96 minfo->hw.DACclk[0] = m; in DAC1064_setpclk()
97 minfo->hw.DACclk[1] = n; in DAC1064_setpclk()
98 minfo->hw.DACclk[2] = p; in DAC1064_setpclk()
101 static void DAC1064_setmclk(struct matrox_fb_info *minfo, int oscinfo, in DAC1064_setmclk() argument
105 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_setmclk()
109 if (minfo->devflags.noinit) { in DAC1064_setmclk()
111 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM); in DAC1064_setmclk()
112 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN); in DAC1064_setmclk()
113 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP); in DAC1064_setmclk()
117 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
132 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
134 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
143 DAC1064_calcclock(minfo, fmem, minfo->max_pixel_clock, &m, &n, &p); in DAC1064_setmclk()
144 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3] = m); in DAC1064_setmclk()
145 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4] = n); in DAC1064_setmclk()
146 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5] = p); in DAC1064_setmclk()
148 if (inDAC1064(minfo, DAC1064_XSYSPLLSTAT) & 0x40) in DAC1064_setmclk()
159 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
161 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
166 static void g450_set_plls(struct matrox_fb_info *minfo) in g450_set_plls() argument
170 struct matrox_hw_state *hw = &minfo->hw; in g450_set_plls()
177 pixelmnp = minfo->crtc1.mnp; in g450_set_plls()
178 videomnp = minfo->crtc2.mnp; in g450_set_plls()
182 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) { in g450_set_plls()
197 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]); in g450_set_plls()
198 matroxfb_g450_setpll_cond(minfo, videomnp, M_VIDEO_PLL); in g450_set_plls()
205 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]); in g450_set_plls()
206 matroxfb_g450_setpll_cond(minfo, pixelmnp, M_PIXEL_PLL_C); in g450_set_plls()
213 pxc = minfo->crtc1.pixclock; in g450_set_plls()
214 if (pxc == 0 || minfo->outputs[2].src == MATROXFB_SRC_CRTC2) { in g450_set_plls()
215 pxc = minfo->crtc2.pixclock; in g450_set_plls()
217 if (minfo->chip == MGA_G550) { in g450_set_plls()
258 void DAC1064_global_init(struct matrox_fb_info *minfo) in DAC1064_global_init() argument
260 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_global_init()
266 if (minfo->devflags.g450dac) { in DAC1064_global_init()
270 switch (minfo->outputs[0].src) { in DAC1064_global_init()
279 switch (minfo->outputs[1].src) { in DAC1064_global_init()
284 if (minfo->outputs[1].mode == MATROXFB_OUTPUT_MODE_MONITOR) { in DAC1064_global_init()
294 switch (minfo->outputs[2].src) { in DAC1064_global_init()
313 g450_set_plls(minfo); in DAC1064_global_init()
317 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1) { in DAC1064_global_init()
320 } else if (minfo->outputs[1].src == MATROXFB_SRC_CRTC2) { in DAC1064_global_init()
322 } else if (minfo->outputs[2].src == MATROXFB_SRC_CRTC1) in DAC1064_global_init()
327 if (minfo->outputs[0].src != MATROXFB_SRC_NONE) in DAC1064_global_init()
332 void DAC1064_global_restore(struct matrox_fb_info *minfo) in DAC1064_global_restore() argument
334 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_global_restore()
336 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]); in DAC1064_global_restore()
337 outDAC1064(minfo, M1064_XMISCCTRL, hw->DACreg[POS1064_XMISCCTRL]); in DAC1064_global_restore()
338 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) { in DAC1064_global_restore()
339 outDAC1064(minfo, 0x20, 0x04); in DAC1064_global_restore()
340 outDAC1064(minfo, 0x1F, minfo->devflags.dfp_type); in DAC1064_global_restore()
341 if (minfo->devflags.g450dac) { in DAC1064_global_restore()
342 outDAC1064(minfo, M1064_XSYNCCTRL, 0xCC); in DAC1064_global_restore()
343 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]); in DAC1064_global_restore()
344 outDAC1064(minfo, M1064_XPANMODE, hw->DACreg[POS1064_XPANMODE]); in DAC1064_global_restore()
345 outDAC1064(minfo, M1064_XOUTPUTCONN, hw->DACreg[POS1064_XOUTPUTCONN]); in DAC1064_global_restore()
350 static int DAC1064_init_1(struct matrox_fb_info *minfo, struct my_timming *m) in DAC1064_init_1() argument
352 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_init_1()
357 switch (minfo->fbcon.var.bits_per_pixel) { in DAC1064_init_1()
363 if (minfo->fbcon.var.green.length == 5) in DAC1064_init_1()
377 hw->DACreg[POS1064_XVREFCTRL] = minfo->features.DAC1064.xvrefctrl; in DAC1064_init_1()
383 DAC1064_global_init(minfo); in DAC1064_init_1()
387 static int DAC1064_init_2(struct matrox_fb_info *minfo, struct my_timming *m) in DAC1064_init_2() argument
389 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_init_2()
393 if (minfo->fbcon.var.bits_per_pixel > 16) { /* 256 entries */ in DAC1064_init_2()
401 } else if (minfo->fbcon.var.bits_per_pixel > 8) { in DAC1064_init_2()
402 if (minfo->fbcon.var.green.length == 5) { /* 0..31, 128..159 */ in DAC1064_init_2()
430 static void DAC1064_restore_1(struct matrox_fb_info *minfo) in DAC1064_restore_1() argument
432 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_restore_1()
440 if ((inDAC1064(minfo, DAC1064_XSYSPLLM) != hw->DACclk[3]) || in DAC1064_restore_1()
441 (inDAC1064(minfo, DAC1064_XSYSPLLN) != hw->DACclk[4]) || in DAC1064_restore_1()
442 (inDAC1064(minfo, DAC1064_XSYSPLLP) != hw->DACclk[5])) { in DAC1064_restore_1()
443 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3]); in DAC1064_restore_1()
444 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4]); in DAC1064_restore_1()
445 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5]); in DAC1064_restore_1()
452 outDAC1064(minfo, MGA1064_DAC_regs[i], hw->DACreg[i]); in DAC1064_restore_1()
456 DAC1064_global_restore(minfo); in DAC1064_restore_1()
461 static void DAC1064_restore_2(struct matrox_fb_info *minfo) in DAC1064_restore_2() argument
472 dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], minfo->hw.DACreg[i]); in DAC1064_restore_2()
477 dprintk("C%02X=%02X ", i, minfo->hw.DACclk[i]); in DAC1064_restore_2()
483 #define minfo ((struct matrox_fb_info*)out) in m1064_compute() macro
489 DAC1064_setpclk(minfo, m->pixclock); in m1064_compute()
494 outDAC1064(minfo, M1064_XPIXPLLCM + i, minfo->hw.DACclk[i]); in m1064_compute()
496 if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40) in m1064_compute()
506 #undef minfo in m1064_compute()
517 #define minfo ((struct matrox_fb_info*)out) in g450_compute() macro
519 …m->mnp = matroxfb_g450_setclk(minfo, m->pixclock, (m->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C … in g450_compute()
521 m->pixclock = g450_mnp2f(minfo, m->mnp); in g450_compute()
524 #undef minfo in g450_compute()
537 static int MGA1064_init(struct matrox_fb_info *minfo, struct my_timming *m) in MGA1064_init() argument
539 struct matrox_hw_state *hw = &minfo->hw; in MGA1064_init()
543 if (DAC1064_init_1(minfo, m)) return 1; in MGA1064_init()
544 if (matroxfb_vgaHWinit(minfo, m)) return 1; in MGA1064_init()
554 if (DAC1064_init_2(minfo, m)) return 1; in MGA1064_init()
560 static int MGAG100_init(struct matrox_fb_info *minfo, struct my_timming *m) in MGAG100_init() argument
562 struct matrox_hw_state *hw = &minfo->hw; in MGAG100_init()
566 if (DAC1064_init_1(minfo, m)) return 1; in MGAG100_init()
568 if (matroxfb_vgaHWinit(minfo, m)) return 1; in MGAG100_init()
578 if (DAC1064_init_2(minfo, m)) return 1; in MGAG100_init()
584 static void MGA1064_ramdac_init(struct matrox_fb_info *minfo) in MGA1064_ramdac_init() argument
590 minfo->features.pll.vco_freq_min = 62000; in MGA1064_ramdac_init()
591 minfo->features.pll.ref_freq = 14318; in MGA1064_ramdac_init()
592 minfo->features.pll.feed_div_min = 100; in MGA1064_ramdac_init()
593 minfo->features.pll.feed_div_max = 127; in MGA1064_ramdac_init()
594 minfo->features.pll.in_div_min = 1; in MGA1064_ramdac_init()
595 minfo->features.pll.in_div_max = 31; in MGA1064_ramdac_init()
596 minfo->features.pll.post_shift_max = 3; in MGA1064_ramdac_init()
597 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_EXTERNAL; in MGA1064_ramdac_init()
599 DAC1064_setmclk(minfo, DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PLL, 133333); in MGA1064_ramdac_init()
611 static void MGAG100_progPixClock(const struct matrox_fb_info *minfo, int flags, in MGAG100_progPixClock() argument
620 outDAC1064(minfo, M1064_XPIXCLKCTRL, inDAC1064(minfo, M1064_XPIXCLKCTRL) | M1064_XPIXCLKCTRL_DIS | in MGAG100_progPixClock()
627 outDAC1064(minfo, reg++, m); in MGAG100_progPixClock()
628 outDAC1064(minfo, reg++, n); in MGAG100_progPixClock()
629 outDAC1064(minfo, reg, p); in MGAG100_progPixClock()
641 if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40) in MGAG100_progPixClock()
647 selClk = inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_SRC_MASK; in MGAG100_progPixClock()
653 outDAC1064(minfo, M1064_XPIXCLKCTRL, selClk); in MGAG100_progPixClock()
654 outDAC1064(minfo, M1064_XPIXCLKCTRL, inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_DIS); in MGAG100_progPixClock()
657 static void MGAG100_setPixClock(const struct matrox_fb_info *minfo, int flags, in MGAG100_setPixClock() argument
664 DAC1064_calcclock(minfo, freq, minfo->max_pixel_clock, &m, &n, &p); in MGAG100_setPixClock()
665 MGAG100_progPixClock(minfo, flags, m, n, p); in MGAG100_setPixClock()
670 static int MGA1064_preinit(struct matrox_fb_info *minfo) in MGA1064_preinit() argument
675 struct matrox_hw_state *hw = &minfo->hw; in MGA1064_preinit()
680 minfo->capable.text = 1; in MGA1064_preinit()
681 minfo->capable.vxres = vxres_mystique; in MGA1064_preinit()
683 minfo->outputs[0].output = &m1064; in MGA1064_preinit()
684 minfo->outputs[0].src = minfo->outputs[0].default_src; in MGA1064_preinit()
685 minfo->outputs[0].data = minfo; in MGA1064_preinit()
686 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR; in MGA1064_preinit()
688 if (minfo->devflags.noinit) in MGA1064_preinit()
692 if (minfo->devflags.novga) in MGA1064_preinit()
694 if (minfo->devflags.nobios) in MGA1064_preinit()
696 if (minfo->devflags.nopciretry) in MGA1064_preinit()
698 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGA1064_preinit()
708 static void MGA1064_reset(struct matrox_fb_info *minfo) in MGA1064_reset() argument
713 MGA1064_ramdac_init(minfo); in MGA1064_reset()
718 static void g450_mclk_init(struct matrox_fb_info *minfo) in g450_mclk_init() argument
721 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4); in g450_mclk_init()
722 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3 & ~0x00300C03); in g450_mclk_init()
723 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_mclk_init()
725 if (((minfo->values.reg.opt3 & 0x000003) == 0x000003) || in g450_mclk_init()
726 ((minfo->values.reg.opt3 & 0x000C00) == 0x000C00) || in g450_mclk_init()
727 ((minfo->values.reg.opt3 & 0x300000) == 0x300000)) { in g450_mclk_init()
728 matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL); in g450_mclk_init()
734 pwr = inDAC1064(minfo, M1064_XPWRCTRL) & ~0x02; in g450_mclk_init()
735 outDAC1064(minfo, M1064_XPWRCTRL, pwr); in g450_mclk_init()
738 matroxfb_g450_setclk(minfo, minfo->values.pll.system, M_SYSTEM_PLL); in g450_mclk_init()
741 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4); in g450_mclk_init()
742 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3); in g450_mclk_init()
743 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_mclk_init()
747 static void g450_memory_init(struct matrox_fb_info *minfo) in g450_memory_init() argument
750 minfo->hw.MXoptionReg &= ~0x001F8000; in g450_memory_init()
751 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_memory_init()
754 minfo->hw.MXoptionReg &= ~0x00207E00; in g450_memory_init()
755 minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt; in g450_memory_init()
756 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_memory_init()
757 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, minfo->values.reg.opt2); in g450_memory_init()
759 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); in g450_memory_init()
762 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc & ~0x80000000U); in g450_memory_init()
763 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); in g450_memory_init()
764 mga_outl(M_MACCESS, minfo->values.reg.maccess); in g450_memory_init()
766 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc | 0x80000000U); in g450_memory_init()
770 if (minfo->values.memory.ddr && (!minfo->values.memory.emrswen || !minfo->values.memory.dll)) { in g450_memory_init()
771 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk & ~0x1000); in g450_memory_init()
773 mga_outl(M_MACCESS, minfo->values.reg.maccess | 0x8000); in g450_memory_init()
777 minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt; in g450_memory_init()
778 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_memory_init()
784 if (minfo->values.reg.mctlwtst != minfo->values.reg.mctlwtst_core) { in g450_memory_init()
785 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst_core); in g450_memory_init()
790 static void g450_preinit(struct matrox_fb_info *minfo) in g450_preinit() argument
797 minfo->hw.MXoptionReg &= 0xC0000100; in g450_preinit()
798 minfo->hw.MXoptionReg |= 0x00000020; in g450_preinit()
799 if (minfo->devflags.novga) in g450_preinit()
800 minfo->hw.MXoptionReg &= ~0x00000100; in g450_preinit()
801 if (minfo->devflags.nobios) in g450_preinit()
802 minfo->hw.MXoptionReg &= ~0x40000000; in g450_preinit()
803 if (minfo->devflags.nopciretry) in g450_preinit()
804 minfo->hw.MXoptionReg |= 0x20000000; in g450_preinit()
805 minfo->hw.MXoptionReg |= minfo->values.reg.opt & 0x03400040; in g450_preinit()
806 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_preinit()
814 curctl = inDAC1064(minfo, M1064_XCURCTRL); in g450_preinit()
815 outDAC1064(minfo, M1064_XCURCTRL, 0); in g450_preinit()
820 g450_mclk_init(minfo); in g450_preinit()
821 g450_memory_init(minfo); in g450_preinit()
824 matroxfb_g450_setclk(minfo, 25175, M_PIXEL_PLL_A); in g450_preinit()
825 matroxfb_g450_setclk(minfo, 28322, M_PIXEL_PLL_B); in g450_preinit()
831 outDAC1064(minfo, M1064_XCURCTRL, curctl); in g450_preinit()
839 static int MGAG100_preinit(struct matrox_fb_info *minfo) in MGAG100_preinit() argument
844 struct matrox_hw_state *hw = &minfo->hw; in MGAG100_preinit()
854 if (minfo->devflags.g450dac) { in MGAG100_preinit()
855 minfo->features.pll.vco_freq_min = 130000; /* my sample: >118 */ in MGAG100_preinit()
857 minfo->features.pll.vco_freq_min = 62000; in MGAG100_preinit()
859 if (!minfo->features.pll.ref_freq) { in MGAG100_preinit()
860 minfo->features.pll.ref_freq = 27000; in MGAG100_preinit()
862 minfo->features.pll.feed_div_min = 7; in MGAG100_preinit()
863 minfo->features.pll.feed_div_max = 127; in MGAG100_preinit()
864 minfo->features.pll.in_div_min = 1; in MGAG100_preinit()
865 minfo->features.pll.in_div_max = 31; in MGAG100_preinit()
866 minfo->features.pll.post_shift_max = 3; in MGAG100_preinit()
867 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_G100_DEFAULT; in MGAG100_preinit()
869 minfo->capable.text = 1; in MGAG100_preinit()
870 minfo->capable.vxres = vxres_g100; in MGAG100_preinit()
871 minfo->capable.plnwt = minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100 in MGAG100_preinit()
872 ? minfo->devflags.sgram : 1; in MGAG100_preinit()
874 if (minfo->devflags.g450dac) { in MGAG100_preinit()
875 minfo->outputs[0].output = &g450out; in MGAG100_preinit()
877 minfo->outputs[0].output = &m1064; in MGAG100_preinit()
879 minfo->outputs[0].src = minfo->outputs[0].default_src; in MGAG100_preinit()
880 minfo->outputs[0].data = minfo; in MGAG100_preinit()
881 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR; in MGAG100_preinit()
883 if (minfo->devflags.g450dac) { in MGAG100_preinit()
888 if (minfo->devflags.noinit) in MGAG100_preinit()
890 if (minfo->devflags.g450dac) { in MGAG100_preinit()
891 g450_preinit(minfo); in MGAG100_preinit()
896 if (minfo->devflags.novga) in MGAG100_preinit()
898 if (minfo->devflags.nobios) in MGAG100_preinit()
900 if (minfo->devflags.nopciretry) in MGAG100_preinit()
902 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_preinit()
903 DAC1064_setmclk(minfo, DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PCI, 133333); in MGAG100_preinit()
905 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100) { in MGAG100_preinit()
906 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50); in MGAG100_preinit()
908 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); in MGAG100_preinit()
911 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_preinit()
912 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); in MGAG100_preinit()
922 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); in MGAG100_preinit()
928 mga_writeb(minfo->video.vbase, 0x0000, 0xAA); in MGAG100_preinit()
929 mga_writeb(minfo->video.vbase, 0x0800, 0x55); in MGAG100_preinit()
930 mga_writeb(minfo->video.vbase, 0x4000, 0x55); in MGAG100_preinit()
932 if (mga_readb(minfo->video.vbase, 0x0000) != 0xAA) { in MGAG100_preinit()
937 } else if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG200) { in MGAG100_preinit()
938 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50); in MGAG100_preinit()
940 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); in MGAG100_preinit()
942 if (minfo->devflags.memtype == -1) in MGAG100_preinit()
943 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00; in MGAG100_preinit()
945 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10; in MGAG100_preinit()
946 if (minfo->devflags.sgram) in MGAG100_preinit()
948 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); in MGAG100_preinit()
949 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); in MGAG100_preinit()
954 mga_outw(M_MEMRDBK, minfo->values.reg.memrdbk); in MGAG100_preinit()
957 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50); in MGAG100_preinit()
960 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); in MGAG100_preinit()
962 if (minfo->devflags.memtype == -1) in MGAG100_preinit()
963 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00; in MGAG100_preinit()
965 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10; in MGAG100_preinit()
966 if (minfo->devflags.sgram) in MGAG100_preinit()
968 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); in MGAG100_preinit()
969 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); in MGAG100_preinit()
974 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); in MGAG100_preinit()
977 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_preinit()
981 static void MGAG100_reset(struct matrox_fb_info *minfo) in MGAG100_reset() argument
984 struct matrox_hw_state *hw = &minfo->hw; in MGAG100_reset()
994 if (b == minfo->pcidev->bus->number) { in MGAG100_reset()
1001 if (!minfo->devflags.noinit) { in MGAG100_reset()
1004 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_reset()
1009 if (minfo->devflags.g450dac) { in MGAG100_reset()
1011 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM); in MGAG100_reset()
1012 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN); in MGAG100_reset()
1013 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP); in MGAG100_reset()
1015 …DAC1064_setmclk(minfo, DAC1064_OPT_RESERVED | DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV1 | DAC1064_OPT_… in MGAG100_reset()
1017 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) { in MGAG100_reset()
1018 if (minfo->devflags.dfp_type == -1) { in MGAG100_reset()
1019 minfo->devflags.dfp_type = inDAC1064(minfo, 0x1F); in MGAG100_reset()
1022 if (minfo->devflags.noinit) in MGAG100_reset()
1024 if (minfo->devflags.g450dac) { in MGAG100_reset()
1026 MGAG100_setPixClock(minfo, 4, 25175); in MGAG100_reset()
1027 MGAG100_setPixClock(minfo, 5, 28322); in MGAG100_reset()
1029 b = inDAC1064(minfo, M1064_XGENIODATA) & ~1; in MGAG100_reset()
1030 outDAC1064(minfo, M1064_XGENIODATA, b); in MGAG100_reset()
1031 b = inDAC1064(minfo, M1064_XGENIOCTRL) | 1; in MGAG100_reset()
1032 outDAC1064(minfo, M1064_XGENIOCTRL, b); in MGAG100_reset()
1039 static void MGA1064_restore(struct matrox_fb_info *minfo) in MGA1064_restore() argument
1042 struct matrox_hw_state *hw = &minfo->hw; in MGA1064_restore()
1050 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGA1064_restore()
1056 DAC1064_restore_1(minfo); in MGA1064_restore()
1057 matroxfb_vgaHWrestore(minfo); in MGA1064_restore()
1058 minfo->crtc1.panpos = -1; in MGA1064_restore()
1061 DAC1064_restore_2(minfo); in MGA1064_restore()
1066 static void MGAG100_restore(struct matrox_fb_info *minfo) in MGAG100_restore() argument
1069 struct matrox_hw_state *hw = &minfo->hw; in MGAG100_restore()
1077 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_restore()
1080 DAC1064_restore_1(minfo); in MGAG100_restore()
1081 matroxfb_vgaHWrestore(minfo); in MGAG100_restore()
1082 if (minfo->devflags.support32MB) in MGAG100_restore()
1084 minfo->crtc1.panpos = -1; in MGAG100_restore()
1087 DAC1064_restore_2(minfo); in MGAG100_restore()