Lines Matching refs:chip
62 RIVA_HW_INST *chip in nv3Busy() argument
65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv3Busy()
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01); in nv3Busy()
70 RIVA_HW_INST *chip in nv4Busy() argument
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv4Busy()
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv4Busy()
78 RIVA_HW_INST *chip in nv10Busy() argument
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv10Busy()
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv10Busy()
87 RIVA_HW_INST *chip, in vgaLockUnlock() argument
92 VGA_WR08(chip->PCIO, 0x3D4, 0x11); in vgaLockUnlock()
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5); in vgaLockUnlock()
96 VGA_WR08(chip->PCIO, 0x3D5, cr11); in vgaLockUnlock()
100 RIVA_HW_INST *chip, in nv3LockUnlock() argument
104 VGA_WR08(chip->PVIO, 0x3C4, 0x06); in nv3LockUnlock()
105 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57); in nv3LockUnlock()
106 vgaLockUnlock(chip, Lock); in nv3LockUnlock()
110 RIVA_HW_INST *chip, in nv4LockUnlock() argument
114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F); in nv4LockUnlock()
115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in nv4LockUnlock()
116 vgaLockUnlock(chip, Lock); in nv4LockUnlock()
121 RIVA_HW_INST *chip, in ShowHideCursor() argument
126 cursor = chip->CurrentState->cursor1; in ShowHideCursor()
127 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | in ShowHideCursor()
129 VGA_WR08(chip->PCIO, 0x3D4, 0x31); in ShowHideCursor()
130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1); in ShowHideCursor()
613 RIVA_HW_INST *chip in nv3UpdateArbitrationSettings() argument
620 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv3UpdateArbitrationSettings()
622 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv3UpdateArbitrationSettings()
627 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv3UpdateArbitrationSettings()
797 RIVA_HW_INST *chip in nv4UpdateArbitrationSettings() argument
804 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv4UpdateArbitrationSettings()
806 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv4UpdateArbitrationSettings()
807 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nv4UpdateArbitrationSettings()
809 NVClk = (N * chip->CrystalFreqKHz / M) >> P; in nv4UpdateArbitrationSettings()
810 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv4UpdateArbitrationSettings()
814 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv4UpdateArbitrationSettings()
1046 RIVA_HW_INST *chip in nv10UpdateArbitrationSettings() argument
1053 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv10UpdateArbitrationSettings()
1055 MClk = (N * chip->CrystalFreqKHz / M) >> P; in nv10UpdateArbitrationSettings()
1056 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nv10UpdateArbitrationSettings()
1058 NVClk = (N * chip->CrystalFreqKHz / M) >> P; in nv10UpdateArbitrationSettings()
1059 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv10UpdateArbitrationSettings()
1063 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ? in nv10UpdateArbitrationSettings()
1065 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv10UpdateArbitrationSettings()
1091 RIVA_HW_INST *chip, in nForceUpdateArbitrationSettings() argument
1110 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nForceUpdateArbitrationSettings()
1112 NVClk = (N * chip->CrystalFreqKHz / M) >> P; in nForceUpdateArbitrationSettings()
1157 RIVA_HW_INST *chip in CalcVClock() argument
1169 if (chip->CrystalFreqKHz == 13500) in CalcVClock()
1172 highM = 13 - (chip->Architecture == NV_ARCH_03); in CalcVClock()
1177 highM = 14 - (chip->Architecture == NV_ARCH_03); in CalcVClock()
1180 highP = 4 - (chip->Architecture == NV_ARCH_03); in CalcVClock()
1184 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz)) in CalcVClock()
1188 N = (VClk << P) * M / chip->CrystalFreqKHz; in CalcVClock()
1190 Freq = (chip->CrystalFreqKHz * N / M) >> P; in CalcVClock()
1217 RIVA_HW_INST *chip, in CalcStateExt() argument
1240 if (!CalcVClock(dotClock, &VClk, &m, &n, &p, chip)) in CalcStateExt()
1243 switch (chip->Architecture) in CalcStateExt()
1250 chip); in CalcStateExt()
1266 chip); in CalcStateExt()
1278 if((chip->Chipset == NV_CHIP_IGEFORCE2) || in CalcStateExt()
1279 (chip->Chipset == NV_CHIP_0x01F0)) in CalcStateExt()
1285 chip, pdev); in CalcStateExt()
1291 chip); in CalcStateExt()
1293 state->cursor0 = 0x80 | (chip->CursorStart >> 17); in CalcStateExt()
1294 state->cursor1 = (chip->CursorStart >> 11) << 2; in CalcStateExt()
1295 state->cursor2 = chip->CursorStart >> 24; in CalcStateExt()
1297 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0); in CalcStateExt()
1305 if((bpp != 8) && (chip->Architecture != NV_ARCH_03)) in CalcStateExt()
1327 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1])
1330 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1])
1333 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1])
1336 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1])
1339 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1])
1343 RIVA_HW_INST *chip in UpdateFifoState() argument
1348 switch (chip->Architecture) in UpdateFifoState()
1352 chip->Tri03 = NULL; in UpdateFifoState()
1353 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); in UpdateFifoState()
1363 chip->Tri03 = NULL; in UpdateFifoState()
1364 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); in UpdateFifoState()
1370 RIVA_HW_INST *chip, in LoadStateExt() argument
1381 switch (chip->Architecture) in LoadStateExt()
1387 NV_WR32(chip->PFB, 0x00000200, state->config); in LoadStateExt()
1397 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1403 chip->Tri03 = NULL; in LoadStateExt()
1409 chip->Tri03 = NULL; in LoadStateExt()
1413 NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03); in LoadStateExt()
1414 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0); in LoadStateExt()
1415 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1); in LoadStateExt()
1416 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2); in LoadStateExt()
1417 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3); in LoadStateExt()
1418 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0); in LoadStateExt()
1419 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1); in LoadStateExt()
1420 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2); in LoadStateExt()
1421 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3); in LoadStateExt()
1427 NV_WR32(chip->PFB, 0x00000200, state->config); in LoadStateExt()
1436 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1441 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1447 chip->Tri03 = NULL; in LoadStateExt()
1453 chip->Tri03 = NULL; in LoadStateExt()
1456 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); in LoadStateExt()
1457 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); in LoadStateExt()
1458 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); in LoadStateExt()
1459 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); in LoadStateExt()
1460 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); in LoadStateExt()
1461 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); in LoadStateExt()
1462 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); in LoadStateExt()
1463 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); in LoadStateExt()
1468 if(chip->twoHeads) { in LoadStateExt()
1469 VGA_WR08(chip->PCIO, 0x03D4, 0x44); in LoadStateExt()
1470 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); in LoadStateExt()
1471 chip->LockUnlock(chip, 0); in LoadStateExt()
1482 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1487 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1493 chip->Tri03 = NULL; in LoadStateExt()
1499 chip->Tri03 = NULL; in LoadStateExt()
1503 if(chip->Architecture == NV_ARCH_10) { in LoadStateExt()
1504 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); in LoadStateExt()
1505 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); in LoadStateExt()
1506 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); in LoadStateExt()
1507 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); in LoadStateExt()
1508 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); in LoadStateExt()
1509 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); in LoadStateExt()
1510 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); in LoadStateExt()
1511 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); in LoadStateExt()
1512 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3); in LoadStateExt()
1514 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0); in LoadStateExt()
1515 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1); in LoadStateExt()
1516 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2); in LoadStateExt()
1517 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3); in LoadStateExt()
1518 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0); in LoadStateExt()
1519 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1); in LoadStateExt()
1520 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2); in LoadStateExt()
1521 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3); in LoadStateExt()
1522 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3); in LoadStateExt()
1523 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3); in LoadStateExt()
1524 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200)); in LoadStateExt()
1525 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204)); in LoadStateExt()
1527 if(chip->twoHeads) { in LoadStateExt()
1528 NV_WR32(chip->PCRTC0, 0x00000860, state->head); in LoadStateExt()
1529 NV_WR32(chip->PCRTC0, 0x00002860, state->head2); in LoadStateExt()
1531 NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25)); in LoadStateExt()
1533 NV_WR32(chip->PMC, 0x00008704, 1); in LoadStateExt()
1534 NV_WR32(chip->PMC, 0x00008140, 0); in LoadStateExt()
1535 NV_WR32(chip->PMC, 0x00008920, 0); in LoadStateExt()
1536 NV_WR32(chip->PMC, 0x00008924, 0); in LoadStateExt()
1537 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); in LoadStateExt()
1538 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); in LoadStateExt()
1539 NV_WR32(chip->PMC, 0x00001588, 0); in LoadStateExt()
1541 NV_WR32(chip->PFB, 0x00000240, 0); in LoadStateExt()
1542 NV_WR32(chip->PFB, 0x00000250, 0); in LoadStateExt()
1543 NV_WR32(chip->PFB, 0x00000260, 0); in LoadStateExt()
1544 NV_WR32(chip->PFB, 0x00000270, 0); in LoadStateExt()
1545 NV_WR32(chip->PFB, 0x00000280, 0); in LoadStateExt()
1546 NV_WR32(chip->PFB, 0x00000290, 0); in LoadStateExt()
1547 NV_WR32(chip->PFB, 0x000002A0, 0); in LoadStateExt()
1548 NV_WR32(chip->PFB, 0x000002B0, 0); in LoadStateExt()
1550 NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240)); in LoadStateExt()
1551 NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244)); in LoadStateExt()
1552 NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248)); in LoadStateExt()
1553 NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C)); in LoadStateExt()
1554 NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250)); in LoadStateExt()
1555 NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254)); in LoadStateExt()
1556 NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258)); in LoadStateExt()
1557 NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C)); in LoadStateExt()
1558 NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260)); in LoadStateExt()
1559 NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264)); in LoadStateExt()
1560 NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268)); in LoadStateExt()
1561 NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C)); in LoadStateExt()
1562 NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270)); in LoadStateExt()
1563 NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274)); in LoadStateExt()
1564 NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278)); in LoadStateExt()
1565 NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C)); in LoadStateExt()
1566 NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280)); in LoadStateExt()
1567 NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284)); in LoadStateExt()
1568 NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288)); in LoadStateExt()
1569 NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C)); in LoadStateExt()
1570 NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290)); in LoadStateExt()
1571 NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294)); in LoadStateExt()
1572 NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298)); in LoadStateExt()
1573 NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C)); in LoadStateExt()
1574 NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0)); in LoadStateExt()
1575 NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4)); in LoadStateExt()
1576 NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8)); in LoadStateExt()
1577 NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC)); in LoadStateExt()
1578 NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0)); in LoadStateExt()
1579 NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4)); in LoadStateExt()
1580 NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8)); in LoadStateExt()
1581 NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC)); in LoadStateExt()
1582 NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000); in LoadStateExt()
1583 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000); in LoadStateExt()
1584 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); in LoadStateExt()
1585 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008); in LoadStateExt()
1586 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200); in LoadStateExt()
1588 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1589 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); in LoadStateExt()
1590 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1591 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800); in LoadStateExt()
1593 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1594 NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000); in LoadStateExt()
1595 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004); in LoadStateExt()
1596 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400); in LoadStateExt()
1598 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1599 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800); in LoadStateExt()
1601 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1602 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00); in LoadStateExt()
1604 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1605 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000); in LoadStateExt()
1607 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1608 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400); in LoadStateExt()
1610 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1611 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800); in LoadStateExt()
1613 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1614 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400); in LoadStateExt()
1616 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1617 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000); in LoadStateExt()
1619 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1620 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); in LoadStateExt()
1622 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); in LoadStateExt()
1624 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig); in LoadStateExt()
1626 if(chip->flatPanel) { in LoadStateExt()
1627 if((chip->Chipset & 0x0ff0) == 0x0110) { in LoadStateExt()
1628 NV_WR32(chip->PRAMDAC, 0x0528, state->dither); in LoadStateExt()
1630 if((chip->Chipset & 0x0ff0) >= 0x0170) { in LoadStateExt()
1631 NV_WR32(chip->PRAMDAC, 0x083C, state->dither); in LoadStateExt()
1634 VGA_WR08(chip->PCIO, 0x03D4, 0x53); in LoadStateExt()
1635 VGA_WR08(chip->PCIO, 0x03D5, 0); in LoadStateExt()
1636 VGA_WR08(chip->PCIO, 0x03D4, 0x54); in LoadStateExt()
1637 VGA_WR08(chip->PCIO, 0x03D5, 0); in LoadStateExt()
1638 VGA_WR08(chip->PCIO, 0x03D4, 0x21); in LoadStateExt()
1639 VGA_WR08(chip->PCIO, 0x03D5, 0xfa); in LoadStateExt()
1642 VGA_WR08(chip->PCIO, 0x03D4, 0x41); in LoadStateExt()
1643 VGA_WR08(chip->PCIO, 0x03D5, state->extra); in LoadStateExt()
1646 UpdateFifoState(chip); in LoadStateExt()
1650 VGA_WR08(chip->PCIO, 0x03D4, 0x19); in LoadStateExt()
1651 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); in LoadStateExt()
1652 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); in LoadStateExt()
1653 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); in LoadStateExt()
1654 VGA_WR08(chip->PCIO, 0x03D4, 0x25); in LoadStateExt()
1655 VGA_WR08(chip->PCIO, 0x03D5, state->screen); in LoadStateExt()
1656 VGA_WR08(chip->PCIO, 0x03D4, 0x28); in LoadStateExt()
1657 VGA_WR08(chip->PCIO, 0x03D5, state->pixel); in LoadStateExt()
1658 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); in LoadStateExt()
1659 VGA_WR08(chip->PCIO, 0x03D5, state->horiz); in LoadStateExt()
1660 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); in LoadStateExt()
1661 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); in LoadStateExt()
1662 VGA_WR08(chip->PCIO, 0x03D4, 0x20); in LoadStateExt()
1663 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); in LoadStateExt()
1664 VGA_WR08(chip->PCIO, 0x03D4, 0x30); in LoadStateExt()
1665 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); in LoadStateExt()
1666 VGA_WR08(chip->PCIO, 0x03D4, 0x31); in LoadStateExt()
1667 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); in LoadStateExt()
1668 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); in LoadStateExt()
1669 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); in LoadStateExt()
1670 VGA_WR08(chip->PCIO, 0x03D4, 0x39); in LoadStateExt()
1671 VGA_WR08(chip->PCIO, 0x03D5, state->interlace); in LoadStateExt()
1673 if(!chip->flatPanel) { in LoadStateExt()
1674 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll); in LoadStateExt()
1675 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel); in LoadStateExt()
1676 if(chip->twoHeads) in LoadStateExt()
1677 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2); in LoadStateExt()
1679 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale); in LoadStateExt()
1681 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general); in LoadStateExt()
1686 NV_WR32(chip->PCRTC, 0x00000140, 0); in LoadStateExt()
1687 NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit); in LoadStateExt()
1691 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); in LoadStateExt()
1695 chip->CurrentState = state; in LoadStateExt()
1699 chip->FifoFreeCount = 0; in LoadStateExt()
1701 chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0); in LoadStateExt()
1705 RIVA_HW_INST *chip, in UnloadStateExt() argument
1712 VGA_WR08(chip->PCIO, 0x03D4, 0x19); in UnloadStateExt()
1713 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1714 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); in UnloadStateExt()
1715 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1716 VGA_WR08(chip->PCIO, 0x03D4, 0x25); in UnloadStateExt()
1717 state->screen = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1718 VGA_WR08(chip->PCIO, 0x03D4, 0x28); in UnloadStateExt()
1719 state->pixel = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1720 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); in UnloadStateExt()
1721 state->horiz = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1722 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); in UnloadStateExt()
1723 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1724 VGA_WR08(chip->PCIO, 0x03D4, 0x20); in UnloadStateExt()
1725 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1726 VGA_WR08(chip->PCIO, 0x03D4, 0x30); in UnloadStateExt()
1727 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1728 VGA_WR08(chip->PCIO, 0x03D4, 0x31); in UnloadStateExt()
1729 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1730 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); in UnloadStateExt()
1731 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1732 VGA_WR08(chip->PCIO, 0x03D4, 0x39); in UnloadStateExt()
1733 state->interlace = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1734 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508); in UnloadStateExt()
1735 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520); in UnloadStateExt()
1736 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C); in UnloadStateExt()
1737 state->general = NV_RD32(chip->PRAMDAC, 0x00000600); in UnloadStateExt()
1738 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848); in UnloadStateExt()
1739 state->config = NV_RD32(chip->PFB, 0x00000200); in UnloadStateExt()
1740 switch (chip->Architecture) in UnloadStateExt()
1743 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630); in UnloadStateExt()
1744 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634); in UnloadStateExt()
1745 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638); in UnloadStateExt()
1746 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C); in UnloadStateExt()
1747 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650); in UnloadStateExt()
1748 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654); in UnloadStateExt()
1749 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658); in UnloadStateExt()
1750 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C); in UnloadStateExt()
1753 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); in UnloadStateExt()
1754 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); in UnloadStateExt()
1755 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); in UnloadStateExt()
1756 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); in UnloadStateExt()
1757 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); in UnloadStateExt()
1758 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); in UnloadStateExt()
1759 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); in UnloadStateExt()
1760 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); in UnloadStateExt()
1765 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); in UnloadStateExt()
1766 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); in UnloadStateExt()
1767 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); in UnloadStateExt()
1768 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); in UnloadStateExt()
1769 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); in UnloadStateExt()
1770 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); in UnloadStateExt()
1771 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); in UnloadStateExt()
1772 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); in UnloadStateExt()
1773 if(chip->twoHeads) { in UnloadStateExt()
1774 state->head = NV_RD32(chip->PCRTC0, 0x00000860); in UnloadStateExt()
1775 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860); in UnloadStateExt()
1776 VGA_WR08(chip->PCIO, 0x03D4, 0x44); in UnloadStateExt()
1777 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1779 VGA_WR08(chip->PCIO, 0x03D4, 0x41); in UnloadStateExt()
1780 state->extra = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1781 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810); in UnloadStateExt()
1783 if((chip->Chipset & 0x0ff0) == 0x0110) { in UnloadStateExt()
1784 state->dither = NV_RD32(chip->PRAMDAC, 0x0528); in UnloadStateExt()
1786 if((chip->Chipset & 0x0ff0) >= 0x0170) { in UnloadStateExt()
1787 state->dither = NV_RD32(chip->PRAMDAC, 0x083C); in UnloadStateExt()
1794 RIVA_HW_INST *chip, in SetStartAddress() argument
1798 NV_WR32(chip->PCRTC, 0x800, start); in SetStartAddress()
1803 RIVA_HW_INST *chip, in SetStartAddress3() argument
1814 chip->LockUnlock(chip, 0); in SetStartAddress3()
1818 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset); in SetStartAddress3()
1820 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset); in SetStartAddress3()
1822 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5); in SetStartAddress3()
1823 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F)); in SetStartAddress3()
1824 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5); in SetStartAddress3()
1825 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60)); in SetStartAddress3()
1829 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A); in SetStartAddress3()
1830 VGA_WR08(chip->PCIO, 0x3C0, 0x13); in SetStartAddress3()
1831 VGA_WR08(chip->PCIO, 0x3C0, pan); in SetStartAddress3()
1835 RIVA_HW_INST *chip, in nv3SetSurfaces2D() argument
1841 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv3SetSurfaces2D()
1843 RIVA_FIFO_FREE(*chip,Tri03,5); in nv3SetSurfaces2D()
1844 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv3SetSurfaces2D()
1846 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv3SetSurfaces2D()
1848 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); in nv3SetSurfaces2D()
1852 RIVA_HW_INST *chip, in nv4SetSurfaces2D() argument
1858 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv4SetSurfaces2D()
1860 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv4SetSurfaces2D()
1862 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv4SetSurfaces2D()
1864 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv4SetSurfaces2D()
1868 RIVA_HW_INST *chip, in nv10SetSurfaces2D() argument
1874 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv10SetSurfaces2D()
1876 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); in nv10SetSurfaces2D()
1878 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); in nv10SetSurfaces2D()
1880 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv10SetSurfaces2D()
1884 RIVA_HW_INST *chip, in nv3SetSurfaces3D() argument
1890 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv3SetSurfaces3D()
1892 RIVA_FIFO_FREE(*chip,Tri03,5); in nv3SetSurfaces3D()
1893 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); in nv3SetSurfaces3D()
1895 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); in nv3SetSurfaces3D()
1897 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); in nv3SetSurfaces3D()
1901 RIVA_HW_INST *chip, in nv4SetSurfaces3D() argument
1907 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); in nv4SetSurfaces3D()
1909 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); in nv4SetSurfaces3D()
1911 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); in nv4SetSurfaces3D()
1913 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv4SetSurfaces3D()
1917 RIVA_HW_INST *chip, in nv10SetSurfaces3D() argument
1923 (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]); in nv10SetSurfaces3D()
1925 RIVA_FIFO_FREE(*chip,Tri03,4); in nv10SetSurfaces3D()
1926 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007); in nv10SetSurfaces3D()
1929 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); in nv10SetSurfaces3D()
1940 RIVA_HW_INST *chip in nv3GetConfig() argument
1946 if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020) in nv3GetConfig()
1948 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in nv3GetConfig()
1949 && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02)) in nv3GetConfig()
1954 chip->RamBandwidthKBytesPerSec = 800000; in nv3GetConfig()
1955 switch (NV_RD32(chip->PFB, 0x00000000) & 0x03) in nv3GetConfig()
1958 chip->RamAmountKBytes = 1024 * 4; in nv3GetConfig()
1961 chip->RamAmountKBytes = 1024 * 2; in nv3GetConfig()
1964 chip->RamAmountKBytes = 1024 * 8; in nv3GetConfig()
1970 chip->RamBandwidthKBytesPerSec = 1000000; in nv3GetConfig()
1971 chip->RamAmountKBytes = 1024 * 8; in nv3GetConfig()
1979 chip->RamBandwidthKBytesPerSec = 1000000; in nv3GetConfig()
1980 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) in nv3GetConfig()
1983 chip->RamAmountKBytes = 1024 * 8; in nv3GetConfig()
1986 chip->RamAmountKBytes = 1024 * 4; in nv3GetConfig()
1989 chip->RamAmountKBytes = 1024 * 2; in nv3GetConfig()
1993 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; in nv3GetConfig()
1994 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]); in nv3GetConfig()
1995 chip->VBlankBit = 0x00000100; in nv3GetConfig()
1996 chip->MaxVClockFreqKHz = 256000; in nv3GetConfig()
2000 chip->Busy = nv3Busy; in nv3GetConfig()
2001 chip->ShowHideCursor = ShowHideCursor; in nv3GetConfig()
2002 chip->LoadStateExt = LoadStateExt; in nv3GetConfig()
2003 chip->UnloadStateExt = UnloadStateExt; in nv3GetConfig()
2004 chip->SetStartAddress = SetStartAddress3; in nv3GetConfig()
2005 chip->SetSurfaces2D = nv3SetSurfaces2D; in nv3GetConfig()
2006 chip->SetSurfaces3D = nv3SetSurfaces3D; in nv3GetConfig()
2007 chip->LockUnlock = nv3LockUnlock; in nv3GetConfig()
2011 RIVA_HW_INST *chip in nv4GetConfig() argument
2017 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) in nv4GetConfig()
2019 chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2 in nv4GetConfig()
2024 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) in nv4GetConfig()
2027 chip->RamAmountKBytes = 1024 * 32; in nv4GetConfig()
2030 chip->RamAmountKBytes = 1024 * 4; in nv4GetConfig()
2033 chip->RamAmountKBytes = 1024 * 8; in nv4GetConfig()
2037 chip->RamAmountKBytes = 1024 * 16; in nv4GetConfig()
2041 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) in nv4GetConfig()
2044 chip->RamBandwidthKBytesPerSec = 800000; in nv4GetConfig()
2047 chip->RamBandwidthKBytesPerSec = 1000000; in nv4GetConfig()
2050 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; in nv4GetConfig()
2051 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); in nv4GetConfig()
2052 chip->VBlankBit = 0x00000001; in nv4GetConfig()
2053 chip->MaxVClockFreqKHz = 350000; in nv4GetConfig()
2057 chip->Busy = nv4Busy; in nv4GetConfig()
2058 chip->ShowHideCursor = ShowHideCursor; in nv4GetConfig()
2059 chip->LoadStateExt = LoadStateExt; in nv4GetConfig()
2060 chip->UnloadStateExt = UnloadStateExt; in nv4GetConfig()
2061 chip->SetStartAddress = SetStartAddress; in nv4GetConfig()
2062 chip->SetSurfaces2D = nv4SetSurfaces2D; in nv4GetConfig()
2063 chip->SetSurfaces3D = nv4SetSurfaces3D; in nv4GetConfig()
2064 chip->LockUnlock = nv4LockUnlock; in nv4GetConfig()
2068 RIVA_HW_INST *chip, in nv10GetConfig() argument
2079 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001)) in nv10GetConfig()
2080 NV_WR32(chip->PMC, 0x00000004, 0x01000001); in nv10GetConfig()
2090 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; in nv10GetConfig()
2095 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; in nv10GetConfig()
2097 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) in nv10GetConfig()
2100 chip->RamAmountKBytes = 1024 * 2; in nv10GetConfig()
2103 chip->RamAmountKBytes = 1024 * 4; in nv10GetConfig()
2106 chip->RamAmountKBytes = 1024 * 8; in nv10GetConfig()
2109 chip->RamAmountKBytes = 1024 * 16; in nv10GetConfig()
2112 chip->RamAmountKBytes = 1024 * 32; in nv10GetConfig()
2115 chip->RamAmountKBytes = 1024 * 64; in nv10GetConfig()
2118 chip->RamAmountKBytes = 1024 * 128; in nv10GetConfig()
2121 chip->RamAmountKBytes = 1024 * 16; in nv10GetConfig()
2125 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) in nv10GetConfig()
2128 chip->RamBandwidthKBytesPerSec = 800000; in nv10GetConfig()
2131 chip->RamBandwidthKBytesPerSec = 1000000; in nv10GetConfig()
2134 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ? in nv10GetConfig()
2148 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22)) in nv10GetConfig()
2149 chip->CrystalFreqKHz = 27000; in nv10GetConfig()
2155 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024; in nv10GetConfig()
2156 chip->CURSOR = NULL; /* can't set this here */ in nv10GetConfig()
2157 chip->VBlankBit = 0x00000001; in nv10GetConfig()
2158 chip->MaxVClockFreqKHz = 350000; in nv10GetConfig()
2162 chip->Busy = nv10Busy; in nv10GetConfig()
2163 chip->ShowHideCursor = ShowHideCursor; in nv10GetConfig()
2164 chip->LoadStateExt = LoadStateExt; in nv10GetConfig()
2165 chip->UnloadStateExt = UnloadStateExt; in nv10GetConfig()
2166 chip->SetStartAddress = SetStartAddress; in nv10GetConfig()
2167 chip->SetSurfaces2D = nv10SetSurfaces2D; in nv10GetConfig()
2168 chip->SetSurfaces3D = nv10SetSurfaces3D; in nv10GetConfig()
2169 chip->LockUnlock = nv4LockUnlock; in nv10GetConfig()
2183 chip->twoHeads = TRUE; in nv10GetConfig()
2186 chip->twoHeads = FALSE; in nv10GetConfig()
2192 RIVA_HW_INST *chip, in RivaGetConfig() argument
2200 chip->Version = RIVA_SW_VERSION; in RivaGetConfig()
2204 switch (chip->Architecture) in RivaGetConfig()
2207 nv3GetConfig(chip); in RivaGetConfig()
2210 nv4GetConfig(chip); in RivaGetConfig()
2215 nv10GetConfig(chip, pdev, chipset); in RivaGetConfig()
2220 chip->Chipset = chipset; in RivaGetConfig()
2224 chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]); in RivaGetConfig()
2225 chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]); in RivaGetConfig()
2226 chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]); in RivaGetConfig()
2227 chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]); in RivaGetConfig()
2228 chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]); in RivaGetConfig()
2229 chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]); in RivaGetConfig()
2230 chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]); in RivaGetConfig()
2231 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in RivaGetConfig()