Lines Matching refs:mask
41 u32 mask = d->mask; in irq_gc_mask_disable_reg() local
44 irq_reg_writel(gc, mask, ct->regs.disable); in irq_gc_mask_disable_reg()
45 *ct->mask_cache &= ~mask; in irq_gc_mask_disable_reg()
60 u32 mask = d->mask; in irq_gc_mask_set_bit() local
63 *ct->mask_cache |= mask; in irq_gc_mask_set_bit()
64 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); in irq_gc_mask_set_bit()
79 u32 mask = d->mask; in irq_gc_mask_clr_bit() local
82 *ct->mask_cache &= ~mask; in irq_gc_mask_clr_bit()
83 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); in irq_gc_mask_clr_bit()
98 u32 mask = d->mask; in irq_gc_unmask_enable_reg() local
101 irq_reg_writel(gc, mask, ct->regs.enable); in irq_gc_unmask_enable_reg()
102 *ct->mask_cache |= mask; in irq_gc_unmask_enable_reg()
114 u32 mask = d->mask; in irq_gc_ack_set_bit() local
117 irq_reg_writel(gc, mask, ct->regs.ack); in irq_gc_ack_set_bit()
129 u32 mask = ~d->mask; in irq_gc_ack_clr_bit() local
132 irq_reg_writel(gc, mask, ct->regs.ack); in irq_gc_ack_clr_bit()
151 u32 mask = d->mask; in irq_gc_mask_disable_and_ack_set() local
154 irq_reg_writel(gc, mask, ct->regs.disable); in irq_gc_mask_disable_and_ack_set()
155 *ct->mask_cache &= ~mask; in irq_gc_mask_disable_and_ack_set()
156 irq_reg_writel(gc, mask, ct->regs.ack); in irq_gc_mask_disable_and_ack_set()
168 u32 mask = d->mask; in irq_gc_eoi() local
171 irq_reg_writel(gc, mask, ct->regs.eoi); in irq_gc_eoi()
186 u32 mask = d->mask; in irq_gc_set_wake() local
188 if (!(mask & gc->wake_enabled)) in irq_gc_set_wake()
193 gc->wake_active |= mask; in irq_gc_set_wake()
195 gc->wake_active &= ~mask; in irq_gc_set_wake()
256 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask; in irq_gc_init_mask_cache()
262 mskreg = ct[i].regs.mask; in irq_gc_init_mask_cache()
484 data->mask = 1 << idx; in irq_map_generic_chip()
557 d->mask = 1 << (i - gc->irq_base); in irq_setup_generic_chip()