Lines Matching refs:index
61 #define MTTY_VFIO_PCI_INDEX_TO_OFFSET(index) \ argument
62 ((u64)(index) << MTTY_VFIO_PCI_OFFSET_SHIFT)
364 static void handle_bar_write(unsigned int index, struct mdev_state *mdev_state, in handle_bar_write() argument
373 if (mdev_state->s[index].dlab) { in handle_bar_write()
374 mdev_state->s[index].divisor |= data; in handle_bar_write()
381 if (mdev_state->s[index].rxtx.count < in handle_bar_write()
382 mdev_state->s[index].max_fifo_size) { in handle_bar_write()
383 mdev_state->s[index].rxtx.fifo[ in handle_bar_write()
384 mdev_state->s[index].rxtx.head] = data; in handle_bar_write()
385 mdev_state->s[index].rxtx.count++; in handle_bar_write()
386 CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.head); in handle_bar_write()
387 mdev_state->s[index].overrun = false; in handle_bar_write()
393 if ((mdev_state->s[index].uart_reg[UART_IER] & in handle_bar_write()
395 (mdev_state->s[index].rxtx.count == in handle_bar_write()
396 mdev_state->s[index].intr_trigger_level)) { in handle_bar_write()
400 index); in handle_bar_write()
406 pr_err("Serial port %d: Buffer Overflow\n", index); in handle_bar_write()
408 mdev_state->s[index].overrun = true; in handle_bar_write()
414 if (mdev_state->s[index].uart_reg[UART_IER] & in handle_bar_write()
423 if (mdev_state->s[index].dlab) in handle_bar_write()
424 mdev_state->s[index].divisor |= (u16)data << 8; in handle_bar_write()
426 mdev_state->s[index].uart_reg[offset] = data; in handle_bar_write()
429 (mdev_state->s[index].rxtx.head == in handle_bar_write()
430 mdev_state->s[index].rxtx.tail)) { in handle_bar_write()
433 index); in handle_bar_write()
444 mdev_state->s[index].fcr = data; in handle_bar_write()
449 mdev_state->s[index].rxtx.count = 0; in handle_bar_write()
450 mdev_state->s[index].rxtx.head = 0; in handle_bar_write()
451 mdev_state->s[index].rxtx.tail = 0; in handle_bar_write()
457 mdev_state->s[index].intr_trigger_level = 1; in handle_bar_write()
461 mdev_state->s[index].intr_trigger_level = 4; in handle_bar_write()
465 mdev_state->s[index].intr_trigger_level = 8; in handle_bar_write()
469 mdev_state->s[index].intr_trigger_level = 14; in handle_bar_write()
478 mdev_state->s[index].intr_trigger_level = 1; in handle_bar_write()
480 mdev_state->s[index].max_fifo_size = MAX_FIFO_SIZE; in handle_bar_write()
482 mdev_state->s[index].max_fifo_size = 1; in handle_bar_write()
483 mdev_state->s[index].intr_trigger_level = 1; in handle_bar_write()
490 mdev_state->s[index].dlab = true; in handle_bar_write()
491 mdev_state->s[index].divisor = 0; in handle_bar_write()
493 mdev_state->s[index].dlab = false; in handle_bar_write()
495 mdev_state->s[index].uart_reg[offset] = data; in handle_bar_write()
499 mdev_state->s[index].uart_reg[offset] = data; in handle_bar_write()
501 if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) && in handle_bar_write()
504 pr_err("Serial port %d: MCR_OUT2 write\n", index); in handle_bar_write()
509 if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) && in handle_bar_write()
512 pr_err("Serial port %d: MCR RTS/DTR write\n", index); in handle_bar_write()
524 mdev_state->s[index].uart_reg[offset] = data; in handle_bar_write()
532 static void handle_bar_read(unsigned int index, struct mdev_state *mdev_state, in handle_bar_read() argument
539 if (mdev_state->s[index].dlab) { in handle_bar_read()
540 *buf = (u8)mdev_state->s[index].divisor; in handle_bar_read()
546 if (mdev_state->s[index].rxtx.head != in handle_bar_read()
547 mdev_state->s[index].rxtx.tail) { in handle_bar_read()
548 *buf = mdev_state->s[index].rxtx.fifo[ in handle_bar_read()
549 mdev_state->s[index].rxtx.tail]; in handle_bar_read()
550 mdev_state->s[index].rxtx.count--; in handle_bar_read()
551 CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.tail); in handle_bar_read()
554 if (mdev_state->s[index].rxtx.head == in handle_bar_read()
555 mdev_state->s[index].rxtx.tail) { in handle_bar_read()
561 pr_err("Serial port %d: Buffer Empty\n", index); in handle_bar_read()
563 if (mdev_state->s[index].uart_reg[UART_IER] & in handle_bar_read()
572 if (mdev_state->s[index].dlab) { in handle_bar_read()
573 *buf = (u8)(mdev_state->s[index].divisor >> 8); in handle_bar_read()
576 *buf = mdev_state->s[index].uart_reg[offset] & 0x0f; in handle_bar_read()
581 u8 ier = mdev_state->s[index].uart_reg[UART_IER]; in handle_bar_read()
586 if ((ier & UART_IER_RLSI) && mdev_state->s[index].overrun) in handle_bar_read()
591 (mdev_state->s[index].rxtx.count >= in handle_bar_read()
592 mdev_state->s[index].intr_trigger_level)) in handle_bar_read()
597 (mdev_state->s[index].rxtx.head == in handle_bar_read()
598 mdev_state->s[index].rxtx.tail)) in handle_bar_read()
603 (mdev_state->s[index].uart_reg[UART_MCR] & in handle_bar_read()
619 *buf = mdev_state->s[index].uart_reg[offset]; in handle_bar_read()
628 if (mdev_state->s[index].rxtx.head != in handle_bar_read()
629 mdev_state->s[index].rxtx.tail) in handle_bar_read()
633 if (mdev_state->s[index].overrun) in handle_bar_read()
637 if (mdev_state->s[index].rxtx.head == in handle_bar_read()
638 mdev_state->s[index].rxtx.tail) in handle_bar_read()
650 if (mdev_state->s[index].uart_reg[UART_MCR] & in handle_bar_read()
652 if (mdev_state->s[index].rxtx.count < in handle_bar_read()
653 mdev_state->s[index].max_fifo_size) in handle_bar_read()
662 *buf = mdev_state->s[index].uart_reg[offset]; in handle_bar_read()
672 int index, pos; in mdev_read_base() local
678 for (index = 0; index <= VFIO_PCI_BAR5_REGION_INDEX; index++) { in mdev_read_base()
680 if (!mdev_state->region_info[index].size) in mdev_read_base()
702 mdev_state->region_info[index].start = ((u64)start_hi << 32) | in mdev_read_base()
710 unsigned int index; in mdev_access() local
719 index = MTTY_VFIO_PCI_OFFSET_TO_INDEX(pos); in mdev_access()
721 switch (index) { in mdev_access()
739 if (!mdev_state->region_info[index].start) in mdev_access()
747 __func__, index, offset, wr_reg[offset], in mdev_access()
748 *buf, mdev_state->s[index].dlab); in mdev_access()
750 handle_bar_write(index, mdev_state, offset, buf, count); in mdev_access()
752 handle_bar_read(index, mdev_state, offset, buf, count); in mdev_access()
757 __func__, index, offset, rd_reg[offset], in mdev_access()
758 *buf, mdev_state->s[index].dlab); in mdev_access()
1557 unsigned int index, unsigned int start, in mtty_set_irqs() argument
1563 switch (index) { in mtty_set_irqs()
1628 mdev_state->irq_index = index; in mtty_set_irqs()
1682 mdev_state->irq_index = index; in mtty_set_irqs()
1727 bar_index = region_info->index; in mtty_get_region_info()
1763 if (irq_info->index != VFIO_PCI_INTX_IRQ_INDEX && in mtty_get_irq_info()
1764 irq_info->index != VFIO_PCI_MSI_IRQ_INDEX) in mtty_get_irq_info()
1770 if (irq_info->index == VFIO_PCI_INTX_IRQ_INDEX) in mtty_get_irq_info()
1855 (info.index >= mdev_state->dev_info.num_irqs)) in mtty_ioctl()
1892 ret = mtty_set_irqs(mdev_state, hdr.flags, hdr.index, hdr.start, in mtty_ioctl()