Lines Matching refs:of
69 of writing includes CHECKPOINT_RESTORE, UML, gVisor, rr. Therefore
72 For complete descriptions of memory sealing, please see
148 of the kernel. If the system does not support Intel(R) TXT, this
151 Intel TXT will provide higher assurance of system configuration and
155 correctly. This level of protection requires a root of trust outside
156 of the kernel itself.
166 See Documentation/arch/x86/intel_txt.rst for a description of how to enable
177 This is the portion of low virtual memory which should be protected
179 can help reduce the impact of kernel NULL pointer bugs.
181 For most ia64, ppc64 and x86 users with lots of address space
182 a value of 65536 is reasonable and should cause no problems.
193 interface. Some of these binaries are statically defined
195 option. However, some of these are dynamically created at
197 To provide an additional layer of security, route all of these
271 string "Ordered list of enabled LSMs"
278 A comma-separated list of LSMs, in initialization order.