Lines Matching refs:bit
35 0x1, 0, ecx, 2, dtes64 , 64-bit DS save area
80 0x1, 0, edx, 17, pse36 , Page Size Extension (36-bit)
92 … 0, edx, 30, ia64 , Legacy IA-64 (Itanium) support bit, now reserved
175 …0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM_INTERRUPT MSR bit 25 is supp…
230 … 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction support
235 …0x7, 0, ecx, 16, la57 , 57-bit linear addresses (five-level pag…
236 …0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/BNDSTX MAWAU value in 64-bit mode
255 … 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported
265 … 0x7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer support
298 0x7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U
299 0x7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S
314 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length of leaf 0xa EBX bit vector
340 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87 (bit 0) supported
341 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE (bit 1) supported
342 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX (bit 2) supported
343 …0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS (bit 3) supported (MPX BND…
344 …0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BNDCSR (bit 4) supported (MPX BNDC…
345 …0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK (bit 5) supported (AVX-512 …
346 …0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256 (bit 6) supported (AVX-5…
347 …0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM (bit 7) supported (AVX-51…
348 …0xd, 0, eax, 9, xcr0_pkru , XCR0.PKRU (bit 9) supported (XSAVE PKRU…
349 …0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET_U (bit 11) supported (CET user…
350 …0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET_S (bit 12) supported (CET supe…
351 …0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TILECONFIG (bit 17) supported (AMX…
352 …0xd, 0, eax, 18, xcr0_tiledata , XCR0.TILEDATA (bit 18) supported (AMX c…
355 …0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.LWP (bit 62) supported (Light-…
372 …63:2, ecx, 0, is_xss_bit , Subleaf N describes an XSS bit, otherwise XCR0 bit
381 … 0xf, 1, eax, 8, l3c_qm_overflow_bit , QM_CTR MSR bit 61 is an overflow bit
417 … 0, edx, 7:0, max_enclave_sz_not64 , Maximum enclave size in non-64-bit mode (log2)
418 …0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum enclave size in 64-bit mode (l…
421 …, 2, secs_attr_mode64bit , ATTRIBUTES.MODE64BIT supported (enclave runs in 64-bit mode)
427 0x12, 1, ecx, 0, xfrm_x87 , Enclave XFRM.X87 (bit 0) supported
428 0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SEE (bit 1) supported
429 0x12, 1, ecx, 2, xfrm_avx , Enclave XFRM.AVX (bit 2) supported
430 …0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (bit 3) supported…
431 …0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XFRM.BNDCSR (bit 4) supported …
432 …0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave XFRM.OPMASK (bit 5) supported …
433 …0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave XFRM.ZMM_Hi256 (bit 6) support…
434 …0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave XFRM.HI16_ZMM (bit 7) supporte…
435 …0x12, 1, ecx, 9, xfrm_pkru , Enclave XFRM.PKRU (bit 9) supported (X…
436 …0x12, 1, ecx, 17, xfrm_tileconfig , Enclave XFRM.TILECONFIG (bit 17) suppo…
437 …0x12, 1, ecx, 18, xfrm_tiledata , Enclave XFRM.TILEDATA (bit 18) support…
553 …0x1c, 0, ecx, 0, lbr_mispredict , Branch misprediction bit supported (IA…
602 …0x23, 0, ebx, 1, zbit , IA32_PERFEVTSELx MSRs Z-bit is support…
645 0x80000001, 0, ecx, 0, lahf_lm , LAHF and SAHF in 64-bit mode
650 0x80000001, 0, ecx, 5, abm , LZCNT advanced bit manipulation
663 0x80000001, 0, ecx, 21, tbm , Trailing bit manipulations
671 … 0, ecx, 30, addr_mask_ext , Breakpoint address mask extension (to bit 31)
688 0x80000001, 0, edx, 17, pse36 , Page Size Extension (36-bit)
689 …80000001, 0, edx, 19, mp , Out-of-spec AMD Multiprocessing bit
697 0x80000001, 0, edx, 29, lm , Long mode (x86-64, 64-bit support)
800 …000008, 0, ebx, 6, mba , Memory Bandwidth Allocation (AMD bit)
811 0x80000008, 0, ebx, 20, no_efer_lmsle , EFER[LMSLE] bit (Long-Mode Segmen…
812 0x80000008, 0, ebx, 21, tlb_flush_nested , INVLPGB RAX[5] bit can be set (ne…
968 0x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV guest mandates 64-bit hypervi…
981 0x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit number used to enable mem…