Lines Matching refs:be
49 then both r0 and r1 must be set to the value 1. This also has the
51 value of r1 must also be equal to 1. In contrast, the weaker rule would
59 lock will not see any changes that will be made by any CPU after it
81 mylock before CPU1(), then both r0 and r1 must be set to the value 0.
83 to 0, then the final value of r0 must also be equal to 0. In contrast,
117 no ordering between the two WRITE_ONCE() calls. It should therefore be
118 no surprise that "r2" can be zero, and a quick herd7 run confirms this.
141 be ordered before the READ_ONCE() from data, thus solving the first
142 problem. The smp_store_release() guarantees that its store will be
156 It is not necessarily the case that accesses ordered by locking will be
183 Counter-intuitive though it might be, it is quite possible to have
184 the final value of r0 be 1, the final value of z be 2, and the final
185 value of r1 be 0. The reason for this surprising outcome is that CPU2()
189 Ordering can be extended to CPUs not holding the lock by careful use
230 It is tempting to allow memory-reference instructions to be pulled
231 into a critical section, but this cannot be allowed in the general case.