Lines Matching refs:UL
47 #define MAIR_ATTR_DEVICE_GRE UL(0x0c)
48 #define MAIR_ATTR_NORMAL_WT UL(0xbb)
67 #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
70 #define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
71 #define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
72 #define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
73 #define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
74 #define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
77 #define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT)
78 #define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT)
79 #define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
80 #define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT)
81 #define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT)
84 #define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
85 #define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
88 #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
89 #define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
90 #define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
91 #define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
94 #define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
95 #define TCR_IPS_52_BITS (UL(6) << TCR_IPS_SHIFT)
96 #define TCR_IPS_48_BITS (UL(5) << TCR_IPS_SHIFT)
97 #define TCR_IPS_40_BITS (UL(2) << TCR_IPS_SHIFT)
98 #define TCR_IPS_36_BITS (UL(1) << TCR_IPS_SHIFT)
100 #define TCR_HA (UL(1) << 39)
101 #define TCR_DS (UL(1) << 59)
116 #define PTE_SHARED (UL(3) << 8) /* SH[1:0], inner shareable */