Lines Matching refs:regs
225 core.regs.pc = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc)); in vcpu_arch_dump()
226 core.regs.ra = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.ra)); in vcpu_arch_dump()
227 core.regs.sp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.sp)); in vcpu_arch_dump()
228 core.regs.gp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.gp)); in vcpu_arch_dump()
229 core.regs.tp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.tp)); in vcpu_arch_dump()
230 core.regs.t0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t0)); in vcpu_arch_dump()
231 core.regs.t1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t1)); in vcpu_arch_dump()
232 core.regs.t2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t2)); in vcpu_arch_dump()
233 core.regs.s0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s0)); in vcpu_arch_dump()
234 core.regs.s1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s1)); in vcpu_arch_dump()
235 core.regs.a0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a0)); in vcpu_arch_dump()
236 core.regs.a1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a1)); in vcpu_arch_dump()
237 core.regs.a2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a2)); in vcpu_arch_dump()
238 core.regs.a3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a3)); in vcpu_arch_dump()
239 core.regs.a4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a4)); in vcpu_arch_dump()
240 core.regs.a5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a5)); in vcpu_arch_dump()
241 core.regs.a6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a6)); in vcpu_arch_dump()
242 core.regs.a7 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a7)); in vcpu_arch_dump()
243 core.regs.s2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s2)); in vcpu_arch_dump()
244 core.regs.s3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s3)); in vcpu_arch_dump()
245 core.regs.s4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s4)); in vcpu_arch_dump()
246 core.regs.s5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s5)); in vcpu_arch_dump()
247 core.regs.s6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s6)); in vcpu_arch_dump()
248 core.regs.s7 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s7)); in vcpu_arch_dump()
249 core.regs.s8 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s8)); in vcpu_arch_dump()
250 core.regs.s9 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s9)); in vcpu_arch_dump()
251 core.regs.s10 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s10)); in vcpu_arch_dump()
252 core.regs.s11 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s11)); in vcpu_arch_dump()
253 core.regs.t3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t3)); in vcpu_arch_dump()
254 core.regs.t4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t4)); in vcpu_arch_dump()
255 core.regs.t5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t5)); in vcpu_arch_dump()
256 core.regs.t6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t6)); in vcpu_arch_dump()
262 core.regs.pc, core.regs.ra, core.regs.sp, core.regs.gp); in vcpu_arch_dump()
265 core.regs.tp, core.regs.t0, core.regs.t1, core.regs.t2); in vcpu_arch_dump()
268 core.regs.s0, core.regs.s1, core.regs.a0, core.regs.a1); in vcpu_arch_dump()
271 core.regs.a2, core.regs.a3, core.regs.a4, core.regs.a5); in vcpu_arch_dump()
274 core.regs.a6, core.regs.a7, core.regs.s2, core.regs.s3); in vcpu_arch_dump()
277 core.regs.s4, core.regs.s5, core.regs.s6, core.regs.s7); in vcpu_arch_dump()
280 core.regs.s8, core.regs.s9, core.regs.s10, core.regs.s11); in vcpu_arch_dump()
283 core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6); in vcpu_arch_dump()
295 vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code); in vcpu_arch_set_entry_point()
328 vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.gp), current_gp); in vm_arch_vcpu_add()
331 vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.sp), stack_vaddr + stack_size); in vm_arch_vcpu_add()
345 uint64_t id = RISCV_CORE_REG(regs.a0); in vcpu_args_set()
356 id = RISCV_CORE_REG(regs.a0); in vcpu_args_set()
359 id = RISCV_CORE_REG(regs.a1); in vcpu_args_set()
362 id = RISCV_CORE_REG(regs.a2); in vcpu_args_set()
365 id = RISCV_CORE_REG(regs.a3); in vcpu_args_set()
368 id = RISCV_CORE_REG(regs.a4); in vcpu_args_set()
371 id = RISCV_CORE_REG(regs.a5); in vcpu_args_set()
374 id = RISCV_CORE_REG(regs.a6); in vcpu_args_set()
377 id = RISCV_CORE_REG(regs.a7); in vcpu_args_set()
405 void route_exception(struct pt_regs *regs) in route_exception() argument
410 ec = regs->cause & ~CAUSE_IRQ_FLAG; in route_exception()
415 if (regs->cause & CAUSE_IRQ_FLAG) { in route_exception()
421 return handlers->exception_handlers[vector][ec](regs); in route_exception()