Lines Matching refs:rdmsr
127 cr0 &= rdmsr(MSR_IA32_VMX_CR0_FIXED1); in prepare_for_vmx_operation()
128 cr0 |= rdmsr(MSR_IA32_VMX_CR0_FIXED0); in prepare_for_vmx_operation()
132 cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1); in prepare_for_vmx_operation()
133 cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0); in prepare_for_vmx_operation()
146 feature_control = rdmsr(MSR_IA32_FEAT_CTL); in prepare_for_vmx_operation()
178 return rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & mask; in ept_vpid_cap_supported()
196 vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS)); in init_vmcs_control_fields()
214 rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); in init_vmcs_control_fields()
216 vmwrite(CPU_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS)); in init_vmcs_control_fields()
224 vmwrite(VM_EXIT_CONTROLS, rdmsr(MSR_IA32_VMX_EXIT_CTLS) | in init_vmcs_control_fields()
228 vmwrite(VM_ENTRY_CONTROLS, rdmsr(MSR_IA32_VMX_ENTRY_CTLS) | in init_vmcs_control_fields()
262 vmwrite(HOST_IA32_PAT, rdmsr(MSR_IA32_CR_PAT)); in init_vmcs_host_state()
264 vmwrite(HOST_IA32_EFER, rdmsr(MSR_EFER)); in init_vmcs_host_state()
267 rdmsr(MSR_CORE_PERF_GLOBAL_CTRL)); in init_vmcs_host_state()
269 vmwrite(HOST_IA32_SYSENTER_CS, rdmsr(MSR_IA32_SYSENTER_CS)); in init_vmcs_host_state()
274 vmwrite(HOST_FS_BASE, rdmsr(MSR_FS_BASE)); in init_vmcs_host_state()
275 vmwrite(HOST_GS_BASE, rdmsr(MSR_GS_BASE)); in init_vmcs_host_state()
280 vmwrite(HOST_IA32_SYSENTER_ESP, rdmsr(MSR_IA32_SYSENTER_ESP)); in init_vmcs_host_state()
281 vmwrite(HOST_IA32_SYSENTER_EIP, rdmsr(MSR_IA32_SYSENTER_EIP)); in init_vmcs_host_state()