Lines Matching refs:vp_set
45 struct hv_vpset vp_set; member
121 ipi_ex->vp_set.format = HV_GENERIC_SET_SPARSE_4K; in sender_guest_code()
122 ipi_ex->vp_set.valid_bank_mask = 1 << 0; in sender_guest_code()
123 ipi_ex->vp_set.bank_contents[0] = BIT(RECEIVER_VCPU_ID_1); in sender_guest_code()
131 hyperv_write_xmm_input(&ipi_ex->vp_set.valid_bank_mask, 1); in sender_guest_code()
143 ipi_ex->vp_set.format = HV_GENERIC_SET_SPARSE_4K; in sender_guest_code()
144 ipi_ex->vp_set.valid_bank_mask = 1 << 1; in sender_guest_code()
145 ipi_ex->vp_set.bank_contents[0] = BIT(RECEIVER_VCPU_ID_2 - 64); in sender_guest_code()
153 hyperv_write_xmm_input(&ipi_ex->vp_set.valid_bank_mask, 1); in sender_guest_code()
165 ipi_ex->vp_set.format = HV_GENERIC_SET_SPARSE_4K; in sender_guest_code()
166 ipi_ex->vp_set.valid_bank_mask = 1 << 1 | 1; in sender_guest_code()
167 ipi_ex->vp_set.bank_contents[0] = BIT(RECEIVER_VCPU_ID_1); in sender_guest_code()
168 ipi_ex->vp_set.bank_contents[1] = BIT(RECEIVER_VCPU_ID_2 - 64); in sender_guest_code()
176 hyperv_write_xmm_input(&ipi_ex->vp_set.valid_bank_mask, 2); in sender_guest_code()
188 ipi_ex->vp_set.format = HV_GENERIC_SET_ALL; in sender_guest_code()
197 ipi_ex->vp_set.valid_bank_mask = 0; in sender_guest_code()
198 hyperv_write_xmm_input(&ipi_ex->vp_set.valid_bank_mask, 2); in sender_guest_code()