| /drivers/accel/ivpu/ |
| A D | ivpu_hw_reg_io.h | 32 #define REG_FLD(REG, FLD) \ argument
34 #define REG_FLD_NUM(REG, FLD, num) \ argument
36 #define REG_GET_FLD(REG, FLD, val) \ argument
38 #define REG_CLR_FLD(REG, FLD, val) \ argument
40 #define REG_SET_FLD(REG, FLD, val) \ argument
42 #define REG_SET_FLD_NUM(REG, FLD, num, val) \ argument
44 #define REG_TEST_FLD(REG, FLD, val) \ argument
46 #define REG_TEST_FLD_NUM(REG, FLD, num, val) \ argument
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| /drivers/gpu/drm/amd/display/dc/hubbub/dcn301/ |
| A D | dcn301_hubbub.c | 29 #define REG(reg)\ macro
40 #define REG(reg)\ macro
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| /drivers/gpu/drm/amd/display/dc/hubbub/dcn201/ |
| A D | dcn201_hubbub.c | 30 #define REG(reg)\ macro
43 #define REG(reg)\ macro
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| /drivers/net/ethernet/freescale/fs_enet/ |
| A D | mii-fec.c | 45 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) argument
46 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) argument
|
| /drivers/scsi/ |
| A D | sun3x_esp.c | 48 #define dma_read32(REG) \ argument
50 #define dma_write32(VAL, REG) \ argument
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| A D | mac_esp.c | 49 #define esp_read8(REG) mac_esp_read8(esp, REG) argument
50 #define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG) argument
|
| A D | sun_esp.c | 32 #define dma_read32(REG) \ argument
34 #define dma_write32(VAL, REG) \ argument
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| /drivers/gpu/drm/amd/display/dc/hubbub/dcn21/ |
| A D | dcn21_hubbub.c | 31 #define REG(reg)\ macro
42 #define REG(reg)\ macro
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| /drivers/gpu/drm/amd/display/dc/hubbub/dcn20/ |
| A D | dcn20_hubbub.c | 31 #define REG(reg)\ macro
41 #define REG(reg)\ macro
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn301/ |
| A D | dcn301_hwseq.c | 35 #define REG(reg)\ macro
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| /drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_opp.c | 30 #define REG(reg) \ macro
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_vmid.c | 31 #define REG(reg)\ macro
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| /drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/ |
| A D | dcn35_mmhubbub.c | 30 #define REG(reg) \ macro
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| /drivers/gpu/drm/amd/display/dc/opp/dcn35/ |
| A D | dcn35_opp.c | 30 #define REG(reg) ((const struct dcn35_opp_registers *)(oppn20->regs))->reg macro
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| /drivers/gpu/drm/amd/display/dc/optc/dcn301/ |
| A D | dcn301_optc.c | 35 #define REG(reg)\ macro
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| /drivers/gpu/drm/amd/display/dc/dwb/dcn35/ |
| A D | dcn35_dwb.c | 27 #define REG(reg)\ macro
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn301/ |
| A D | dcn301_dccg.c | 33 #define REG(reg) \ macro
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| /drivers/gpu/drm/amd/display/dc/hpo/dcn32/ |
| A D | dcn32_hpo_dp_link_encoder.c | 34 #define REG(reg)\ macro
|
| /drivers/gpu/drm/amd/display/dc/bios/ |
| A D | bios_parser_helper.c | 50 #define REG(reg)\ macro
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| /drivers/gpu/drm/amd/display/dc/dccg/dcn201/ |
| A D | dcn201_dccg.c | 34 #define REG(reg) \ macro
|
| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_afmt.c | 36 #define REG(reg)\ macro
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| A D | dcn31_vpg.c | 35 #define REG(reg)\ macro
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| /drivers/gpu/drm/amd/display/dc/hwss/dce120/ |
| A D | dce120_hwseq.c | 43 #define REG(reg)\ macro
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| /drivers/regulator/ |
| A D | rn5t618-regulator.c | 25 #define REG(rid, ereg, emask, vreg, vmask, min, max, step) \ macro
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| /drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| A D | hw_translate_dce120.c | 51 #define REG(reg_name)\ macro
|