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Searched defs:__mask (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/i915/
A Di915_reg_defs.h41 #define REG_FIELD_PREP(__mask, __val) \ argument
58 #define REG_FIELD_PREP8(__mask, __val) \ argument
75 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) argument
87 #define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val)) argument
101 #define REG_FIELD_PREP16(__mask, __val) \ argument
175 #define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val)) argument
/drivers/net/wireless/ralink/rt2x00/
A Drt2x00reg.h206 #define FIELD_CHECK(__mask, __type) \ argument
211 #define FIELD8(__mask) \ argument
219 #define FIELD16(__mask) \ argument
227 #define FIELD32(__mask) \ argument
/drivers/pinctrl/spear/
A Dpinctrl-spear.h61 #define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste) \ argument
70 #define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \ argument
/drivers/gpu/drm/i915/display/
A Dintel_display.h88 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \ argument
194 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ argument
202 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ argument
A Dintel_display_power.h166 #define for_each_power_domain(__domain, __mask) \ argument
/drivers/mmc/core/
A Dmmc_ops.h63 const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; in unstuff_bits() local
/drivers/gpu/drm/panthor/
A Dpanthor_fw.h424 #define panthor_fw_toggle_reqs(__iface, __in_reg, __out_reg, __mask) \ argument
450 #define panthor_fw_update_reqs(__iface, __in_reg, __val, __mask) \ argument
/drivers/gpu/drm/nouveau/dispnv04/i2c/
A Dch7006_priv.h142 #define __mask(src, bitfield) \ macro
/drivers/net/ethernet/broadcom/bnx2x/
A Dbnx2x.h97 #define DP(__mask, fmt, ...) \ argument
103 #define DP_AND(__mask, fmt, ...) \ argument
109 #define DP_CONT(__mask, fmt, ...) \ argument

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