| /drivers/reset/sti/ |
| A D | reset-stih407.c | 18 #define STIH407_PDN_0(_bit) \ argument
20 #define STIH407_PDN_1(_bit) \ argument
22 #define STIH407_PDN_ETH(_bit, _stat) \ argument
57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
60 #define STIH407_SRST_SBC(_reg, _bit) \ argument
63 #define STIH407_SRST_LPM(_reg, _bit) \ argument
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| /drivers/clk/meson/ |
| A D | clk-regmap.h | 121 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
136 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
139 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
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| A D | c3-peripherals.c | 167 #define C3_CLK_GATE(_name, _reg, _bit, _fw_name, _ops, _flags) \ argument
184 #define C3_SYS_GATE(_name, _reg, _bit, _flags) \ argument
188 #define C3_SYS_GATE_RO(_name, _reg, _bit) \ argument
293 #define C3_AXI_GATE(_name, _reg, _bit, _flags) \ argument
561 #define AML_PWM_CLK_GATE(_name, _reg, _bit) { \ argument
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| A D | gxbb-aoclk.c | 26 #define GXBB_AO_GATE(_name, _bit) \ argument
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| A D | axg-aoclk.c | 37 #define AXG_AO_GATE(_name, _bit) \ argument
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| A D | g12a-aoclk.c | 46 #define AXG_AO_GATE(_name, _reg, _bit) \ argument
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| A D | meson8b.c | 2745 #define MESON_GATE(_name, _reg, _bit) \ argument
2820 #define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \ argument
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| A D | axg-audio.c | 80 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ argument
126 #define AUD_PCLK_GATE(_name, _reg, _bit) { \ argument
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| A D | a1-peripherals.c | 1843 #define MESON_GATE(_name, _reg, _bit) \ argument
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| A D | g12a.c | 4411 #define MESON_GATE(_name, _reg, _bit) \ argument
4414 #define MESON_GATE_RO(_name, _reg, _bit) \ argument
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| A D | axg.c | 1918 #define MESON_GATE(_name, _reg, _bit) \ argument
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| /drivers/clk/renesas/ |
| A D | rzg2l-cpg.h | 221 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, _is_coupled) \ argument
232 #define DEF_MOD(_name, _id, _parent, _off, _bit, _mstop_conf) \ argument
235 #define DEF_COUPLED(_name, _id, _parent, _off, _bit, _mstop_conf) \ argument
251 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ argument
257 #define DEF_RST(_id, _off, _bit) \ argument
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| /drivers/clk/mvebu/ |
| A D | armada-37xx-periph.c | 129 #define PERIPH_GATE(_name, _bit) \ argument
181 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
186 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ argument
191 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ argument
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| /drivers/reset/ |
| A D | reset-uniphier.c | 27 #define UNIPHIER_RESET(_id, _reg, _bit) \ argument
34 #define UNIPHIER_RESETX(_id, _reg, _bit) \ argument
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| /drivers/memory/tegra/ |
| A D | tegra210.c | 1234 #define TEGRA210_MC_RESET(_name, _control, _status, _bit) \ argument
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| A D | tegra114.c | 1076 #define TEGRA114_MC_RESET(_name, _control, _status, _bit) \ argument
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| A D | tegra124.c | 1112 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \ argument
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| A D | tegra30.c | 1189 #define TEGRA30_MC_RESET(_name, _control, _status, _bit) \ argument
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| A D | tegra20.c | 251 #define TEGRA20_MC_RESET(_name, _control, _status, _reset, _bit) \ argument
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| /drivers/net/ethernet/mellanox/mlx5/core/steering/hws/ |
| A D | internal.h | 36 #define IS_BIT_SET(_value, _bit) ((_value) & (1ULL << (_bit))) argument
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| /drivers/clk/bcm/ |
| A D | clk-kona.h | 91 #define POLICY(_offset, _bit) \ argument
375 #define TRIGGER(_offset, _bit) \ argument
434 #define CCU_LVM_EN(_offset, _bit) \ argument
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| /drivers/pinctrl/mediatek/ |
| A D | pinctrl-mt2701.c | 30 #define MTK_PINMUX_SPEC(_pin, _offset, _bit) \ argument
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| A D | pinctrl-mtk-common.h | 109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
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| /drivers/clk/ |
| A D | clk-k210.c | 49 #define K210_GATE(_reg, _bit) \ argument
59 #define K210_MUX(_reg, _bit) \ argument
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| /drivers/clk/uniphier/ |
| A D | clk-uniphier.h | 95 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ argument
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