1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <linux/pci.h>
28
29 #include <drm/drm_edid.h>
30 #include <drm/amdgpu_drm.h>
31 #include "amdgpu.h"
32 #include "amdgpu_i2c.h"
33 #include "amdgpu_atombios.h"
34 #include "atom.h"
35 #include "atombios_dp.h"
36 #include "atombios_i2c.h"
37
38 /* bit banging i2c */
amdgpu_i2c_pre_xfer(struct i2c_adapter * i2c_adap)39 static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap)
40 {
41 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
42 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
43 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
44 uint32_t temp;
45
46 mutex_lock(&i2c->mutex);
47
48 /* switch the pads to ddc mode */
49 if (rec->hw_capable) {
50 temp = RREG32(rec->mask_clk_reg);
51 temp &= ~(1 << 16);
52 WREG32(rec->mask_clk_reg, temp);
53 }
54
55 /* clear the output pin values */
56 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
57 WREG32(rec->a_clk_reg, temp);
58
59 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
60 WREG32(rec->a_data_reg, temp);
61
62 /* set the pins to input */
63 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
64 WREG32(rec->en_clk_reg, temp);
65
66 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
67 WREG32(rec->en_data_reg, temp);
68
69 /* mask the gpio pins for software use */
70 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
71 WREG32(rec->mask_clk_reg, temp);
72 temp = RREG32(rec->mask_clk_reg);
73
74 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
75 WREG32(rec->mask_data_reg, temp);
76 temp = RREG32(rec->mask_data_reg);
77
78 return 0;
79 }
80
amdgpu_i2c_post_xfer(struct i2c_adapter * i2c_adap)81 static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap)
82 {
83 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
84 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
85 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
86 uint32_t temp;
87
88 /* unmask the gpio pins for software use */
89 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
90 WREG32(rec->mask_clk_reg, temp);
91 temp = RREG32(rec->mask_clk_reg);
92
93 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
94 WREG32(rec->mask_data_reg, temp);
95 temp = RREG32(rec->mask_data_reg);
96
97 mutex_unlock(&i2c->mutex);
98 }
99
amdgpu_i2c_get_clock(void * i2c_priv)100 static int amdgpu_i2c_get_clock(void *i2c_priv)
101 {
102 struct amdgpu_i2c_chan *i2c = i2c_priv;
103 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
104 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
105 uint32_t val;
106
107 /* read the value off the pin */
108 val = RREG32(rec->y_clk_reg);
109 val &= rec->y_clk_mask;
110
111 return (val != 0);
112 }
113
114
amdgpu_i2c_get_data(void * i2c_priv)115 static int amdgpu_i2c_get_data(void *i2c_priv)
116 {
117 struct amdgpu_i2c_chan *i2c = i2c_priv;
118 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
119 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
120 uint32_t val;
121
122 /* read the value off the pin */
123 val = RREG32(rec->y_data_reg);
124 val &= rec->y_data_mask;
125
126 return (val != 0);
127 }
128
amdgpu_i2c_set_clock(void * i2c_priv,int clock)129 static void amdgpu_i2c_set_clock(void *i2c_priv, int clock)
130 {
131 struct amdgpu_i2c_chan *i2c = i2c_priv;
132 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
133 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
134 uint32_t val;
135
136 /* set pin direction */
137 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
138 val |= clock ? 0 : rec->en_clk_mask;
139 WREG32(rec->en_clk_reg, val);
140 }
141
amdgpu_i2c_set_data(void * i2c_priv,int data)142 static void amdgpu_i2c_set_data(void *i2c_priv, int data)
143 {
144 struct amdgpu_i2c_chan *i2c = i2c_priv;
145 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
146 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
147 uint32_t val;
148
149 /* set pin direction */
150 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
151 val |= data ? 0 : rec->en_data_mask;
152 WREG32(rec->en_data_reg, val);
153 }
154
155 static const struct i2c_algorithm amdgpu_atombios_i2c_algo = {
156 .master_xfer = amdgpu_atombios_i2c_xfer,
157 .functionality = amdgpu_atombios_i2c_func,
158 };
159
amdgpu_i2c_create(struct drm_device * dev,const struct amdgpu_i2c_bus_rec * rec,const char * name)160 struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev,
161 const struct amdgpu_i2c_bus_rec *rec,
162 const char *name)
163 {
164 struct amdgpu_i2c_chan *i2c;
165 int ret;
166
167 /* don't add the mm_i2c bus unless hw_i2c is enabled */
168 if (rec->mm_i2c && (amdgpu_hw_i2c == 0))
169 return NULL;
170
171 i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL);
172 if (i2c == NULL)
173 return NULL;
174
175 i2c->rec = *rec;
176 i2c->adapter.owner = THIS_MODULE;
177 i2c->adapter.dev.parent = dev->dev;
178 i2c->dev = dev;
179 i2c_set_adapdata(&i2c->adapter, i2c);
180 mutex_init(&i2c->mutex);
181 if (rec->hw_capable &&
182 amdgpu_hw_i2c) {
183 /* hw i2c using atom */
184 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
185 "AMDGPU i2c hw bus %s", name);
186 i2c->adapter.algo = &amdgpu_atombios_i2c_algo;
187 ret = i2c_add_adapter(&i2c->adapter);
188 if (ret)
189 goto out_free;
190 } else {
191 /* set the amdgpu bit adapter */
192 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
193 "AMDGPU i2c bit bus %s", name);
194 i2c->adapter.algo_data = &i2c->bit;
195 i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer;
196 i2c->bit.post_xfer = amdgpu_i2c_post_xfer;
197 i2c->bit.setsda = amdgpu_i2c_set_data;
198 i2c->bit.setscl = amdgpu_i2c_set_clock;
199 i2c->bit.getsda = amdgpu_i2c_get_data;
200 i2c->bit.getscl = amdgpu_i2c_get_clock;
201 i2c->bit.udelay = 10;
202 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */
203 i2c->bit.data = i2c;
204 ret = i2c_bit_add_bus(&i2c->adapter);
205 if (ret) {
206 DRM_ERROR("Failed to register bit i2c %s\n", name);
207 goto out_free;
208 }
209 }
210
211 return i2c;
212 out_free:
213 kfree(i2c);
214 return NULL;
215
216 }
217
amdgpu_i2c_destroy(struct amdgpu_i2c_chan * i2c)218 void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c)
219 {
220 if (!i2c)
221 return;
222 WARN_ON(i2c->has_aux);
223 i2c_del_adapter(&i2c->adapter);
224 kfree(i2c);
225 }
226
amdgpu_i2c_init(struct amdgpu_device * adev)227 void amdgpu_i2c_init(struct amdgpu_device *adev)
228 {
229 if (!adev->is_atom_fw) {
230 if (!amdgpu_device_has_dc_support(adev)) {
231 amdgpu_atombios_i2c_init(adev);
232 } else {
233 switch (adev->asic_type) {
234 case CHIP_POLARIS10:
235 case CHIP_POLARIS11:
236 case CHIP_POLARIS12:
237 amdgpu_atombios_oem_i2c_init(adev, 0x97);
238 break;
239 default:
240 break;
241 }
242 }
243 }
244 }
245
246 /* remove all the buses */
amdgpu_i2c_fini(struct amdgpu_device * adev)247 void amdgpu_i2c_fini(struct amdgpu_device *adev)
248 {
249 int i;
250
251 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
252 if (adev->i2c_bus[i]) {
253 amdgpu_i2c_destroy(adev->i2c_bus[i]);
254 adev->i2c_bus[i] = NULL;
255 }
256 }
257 }
258
259 /* looks up bus based on id */
260 struct amdgpu_i2c_chan *
amdgpu_i2c_lookup(struct amdgpu_device * adev,const struct amdgpu_i2c_bus_rec * i2c_bus)261 amdgpu_i2c_lookup(struct amdgpu_device *adev,
262 const struct amdgpu_i2c_bus_rec *i2c_bus)
263 {
264 int i;
265
266 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
267 if (adev->i2c_bus[i] &&
268 (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
269 return adev->i2c_bus[i];
270 }
271 }
272 return NULL;
273 }
274
amdgpu_i2c_get_byte(struct amdgpu_i2c_chan * i2c_bus,u8 slave_addr,u8 addr,u8 * val)275 static int amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus,
276 u8 slave_addr,
277 u8 addr,
278 u8 *val)
279 {
280 u8 out_buf[2];
281 u8 in_buf[2];
282 struct i2c_msg msgs[] = {
283 {
284 .addr = slave_addr,
285 .flags = 0,
286 .len = 1,
287 .buf = out_buf,
288 },
289 {
290 .addr = slave_addr,
291 .flags = I2C_M_RD,
292 .len = 1,
293 .buf = in_buf,
294 }
295 };
296
297 out_buf[0] = addr;
298 out_buf[1] = 0;
299
300 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) != 2) {
301 DRM_DEBUG("i2c 0x%02x read failed\n", addr);
302 return -EIO;
303 }
304
305 *val = in_buf[0];
306 DRM_DEBUG("val = 0x%02x\n", *val);
307
308 return 0;
309 }
310
amdgpu_i2c_put_byte(struct amdgpu_i2c_chan * i2c_bus,u8 slave_addr,u8 addr,u8 val)311 static int amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus,
312 u8 slave_addr,
313 u8 addr,
314 u8 val)
315 {
316 uint8_t out_buf[2];
317 struct i2c_msg msg = {
318 .addr = slave_addr,
319 .flags = 0,
320 .len = 2,
321 .buf = out_buf,
322 };
323
324 out_buf[0] = addr;
325 out_buf[1] = val;
326
327 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) {
328 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", addr, val);
329 return -EIO;
330 }
331
332 return 0;
333 }
334
335 /* ddc router switching */
336 void
amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector * amdgpu_connector)337 amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector)
338 {
339 u8 val = 0;
340
341 if (!amdgpu_connector->router.ddc_valid)
342 return;
343
344 if (!amdgpu_connector->router_bus)
345 return;
346
347 if (amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
348 amdgpu_connector->router.i2c_addr,
349 0x3, &val))
350 return;
351 val &= ~amdgpu_connector->router.ddc_mux_control_pin;
352 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
353 amdgpu_connector->router.i2c_addr,
354 0x3, val);
355 if (amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
356 amdgpu_connector->router.i2c_addr,
357 0x1, &val))
358 return;
359 val &= ~amdgpu_connector->router.ddc_mux_control_pin;
360 val |= amdgpu_connector->router.ddc_mux_state;
361 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
362 amdgpu_connector->router.i2c_addr,
363 0x1, val);
364 }
365
366 /* clock/data router switching */
367 void
amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector * amdgpu_connector)368 amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *amdgpu_connector)
369 {
370 u8 val;
371
372 if (!amdgpu_connector->router.cd_valid)
373 return;
374
375 if (!amdgpu_connector->router_bus)
376 return;
377
378 if (amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
379 amdgpu_connector->router.i2c_addr,
380 0x3, &val))
381 return;
382 val &= ~amdgpu_connector->router.cd_mux_control_pin;
383 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
384 amdgpu_connector->router.i2c_addr,
385 0x3, val);
386 if (amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
387 amdgpu_connector->router.i2c_addr,
388 0x1, &val))
389 return;
390 val &= ~amdgpu_connector->router.cd_mux_control_pin;
391 val |= amdgpu_connector->router.cd_mux_state;
392 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
393 amdgpu_connector->router.i2c_addr,
394 0x1, val);
395 }
396