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/drivers/net/wireless/quantenna/qtnfmac/pcie/
A Dpearl_pcie_regs.h8 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00) argument
9 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04) argument
21 #define PCIE_HDP_INT_EN(base) ((base) + 0x2c3c) argument
35 #define PCIE_HDP_CFG0(base) ((base) + 0x2c80) argument
36 #define PCIE_HDP_CFG1(base) ((base) + 0x2c84) argument
37 #define PCIE_HDP_CFG2(base) ((base) + 0x2c88) argument
38 #define PCIE_HDP_CFG3(base) ((base) + 0x2c8c) argument
39 #define PCIE_HDP_CFG4(base) ((base) + 0x2c90) argument
47 #define PCIE_INT(base) ((base) + 0x2cb0) argument
51 #define PCIE_PRI_CFG(base) ((base) + 0x2cc0) argument
[all …]
A Dtopaz_pcie_regs.h8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc) argument
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4) argument
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8) argument
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc) argument
15 #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310) argument
16 #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319) argument
17 #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c) argument
24 #define TOPAZ_LH_IPC4_INT(base) ((base) + 0x13C) argument
25 #define TOPAZ_LH_IPC4_INT_MASK(base) ((base) + 0x140) argument
34 #define TOPAZ_CTL_M2L_INT(base) ((base) + 0x2C) argument
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/drivers/gpu/drm/i915/gt/
A Dintel_engine_regs.h11 #define RING_EXCC(base) _MMIO((base) + 0x28) argument
12 #define RING_TAIL(base) _MMIO((base) + 0x30) argument
14 #define RING_HEAD(base) _MMIO((base) + 0x34) argument
19 #define RING_START(base) _MMIO((base) + 0x38) argument
20 #define RING_CTL(base) _MMIO((base) + 0x3c) argument
32 #define RING_SYNC_0(base) _MMIO((base) + 0x40) argument
68 #define IPEIR(base) _MMIO((base) + 0x88) argument
69 #define IPEHR(base) _MMIO((base) + 0x8c) argument
70 #define RING_ID(base) _MMIO((base) + 0x8c) argument
87 #define ACTHD(base) _MMIO((base) + 0xc8) argument
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/drivers/gpu/drm/xe/regs/
A Dxe_engine_regs.h46 #define ENGINE_ID(base) XE_REG((base) + 0x8c) argument
50 #define RING_TAIL(base) XE_REG((base) + 0x30) argument
53 #define RING_HEAD(base) XE_REG((base) + 0x34) argument
56 #define RING_START(base) XE_REG((base) + 0x38) argument
58 #define RING_CTL(base) XE_REG((base) + 0x3c) argument
73 #define RING_IPEHR(base) XE_REG((base) + 0x68) argument
75 #define RING_ACTHD(base) XE_REG((base) + 0x74) argument
86 #define RING_IMR(base) XE_REG((base) + 0xa8) argument
91 #define RING_EIR(base) XE_REG((base) + 0xb0) argument
92 #define RING_EMR(base) XE_REG((base) + 0xb4) argument
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A Dxe_gsc_regs.h23 #define HECI_H_CSR(base) XE_REG((base) + 0x4) argument
34 #define HECI_FWSTS1(base) XE_REG((base) + 0xc40) argument
39 #define HECI_FWSTS2(base) XE_REG((base) + 0xc48) argument
40 #define HECI_FWSTS3(base) XE_REG((base) + 0xc60) argument
41 #define HECI_FWSTS4(base) XE_REG((base) + 0xc64) argument
42 #define HECI_FWSTS5(base) XE_REG((base) + 0xc68) argument
44 #define HECI_FWSTS6(base) XE_REG((base) + 0xc6c) argument
46 #define HECI_H_GS1(base) XE_REG((base) + 0xc4c) argument
/drivers/gpu/drm/sun4i/
A Dsun8i_vi_scaler.h30 #define SUN8I_SCALER_VSU_CTRL(base) ((base) + 0x0) argument
32 #define SUN50I_SCALER_VSU_DIR_THR(base) ((base) + 0x20) argument
36 #define SUN8I_SCALER_VSU_OUTSIZE(base) ((base) + 0x40) argument
37 #define SUN8I_SCALER_VSU_YINSIZE(base) ((base) + 0x80) argument
38 #define SUN8I_SCALER_VSU_YHSTEP(base) ((base) + 0x88) argument
39 #define SUN8I_SCALER_VSU_YVSTEP(base) ((base) + 0x8c) argument
40 #define SUN8I_SCALER_VSU_YHPHASE(base) ((base) + 0x90) argument
41 #define SUN8I_SCALER_VSU_YVPHASE(base) ((base) + 0x98) argument
42 #define SUN8I_SCALER_VSU_CINSIZE(base) ((base) + 0xc0) argument
43 #define SUN8I_SCALER_VSU_CHSTEP(base) ((base) + 0xc8) argument
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A Dsun8i_ui_layer.h17 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \ argument
19 #define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \ argument
21 #define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \ argument
23 #define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \ argument
25 #define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \ argument
27 #define SUN8I_MIXER_CHAN_UI_LAYER_BOT_LADDR(base, layer) \ argument
29 #define SUN8I_MIXER_CHAN_UI_LAYER_FCOLOR(base, layer) \ argument
31 #define SUN8I_MIXER_CHAN_UI_TOP_HADDR(base) \ argument
33 #define SUN8I_MIXER_CHAN_UI_BOT_HADDR(base) \ argument
35 #define SUN8I_MIXER_CHAN_UI_OVL_SIZE(base) \ argument
A Dsun8i_vi_layer.h11 #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \ argument
13 #define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \ argument
15 #define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \ argument
17 #define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \ argument
19 #define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \ argument
21 #define SUN8I_MIXER_CHAN_VI_OVL_SIZE(base) \ argument
23 #define SUN8I_MIXER_CHAN_VI_HDS_Y(base) \ argument
25 #define SUN8I_MIXER_CHAN_VI_HDS_UV(base) \ argument
27 #define SUN8I_MIXER_CHAN_VI_VDS_Y(base) \ argument
29 #define SUN8I_MIXER_CHAN_VI_VDS_UV(base) \ argument
A Dsun8i_ui_scaler.h26 #define SUN8I_SCALER_GSU_CTRL(base) ((base) + 0x0) argument
27 #define SUN8I_SCALER_GSU_OUTSIZE(base) ((base) + 0x40) argument
28 #define SUN8I_SCALER_GSU_INSIZE(base) ((base) + 0x80) argument
29 #define SUN8I_SCALER_GSU_HSTEP(base) ((base) + 0x88) argument
30 #define SUN8I_SCALER_GSU_VSTEP(base) ((base) + 0x8c) argument
31 #define SUN8I_SCALER_GSU_HPHASE(base) ((base) + 0x90) argument
32 #define SUN8I_SCALER_GSU_VPHASE(base) ((base) + 0x98) argument
33 #define SUN8I_SCALER_GSU_HCOEFF(base, index) ((base) + 0x200 + 0x4 * (index)) argument
/drivers/scsi/
A Dnsp32_io.h12 static inline void nsp32_write1(unsigned int base, in nsp32_write1()
19 static inline unsigned char nsp32_read1(unsigned int base, in nsp32_read1()
25 static inline void nsp32_write2(unsigned int base, in nsp32_write2()
32 static inline unsigned short nsp32_read2(unsigned int base, in nsp32_read2()
38 static inline void nsp32_write4(unsigned int base, in nsp32_write4()
45 static inline unsigned long nsp32_read4(unsigned int base, in nsp32_read4()
53 static inline void nsp32_mmio_write1(unsigned long base, in nsp32_mmio_write1()
74 static inline void nsp32_mmio_write2(unsigned long base, in nsp32_mmio_write2()
95 static inline void nsp32_mmio_write4(unsigned long base, in nsp32_mmio_write4()
125 static inline void nsp32_index_write1(unsigned int base, in nsp32_index_write1()
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A Daha1740.h19 #define HID0(base) (base + 0x0) argument
20 #define HID1(base) (base + 0x1) argument
21 #define HID2(base) (base + 0x2) argument
22 #define HID3(base) (base + 0x3) argument
23 #define EBCNTRL(base) (base + 0x4) argument
24 #define PORTADR(base) (base + 0x40) argument
26 #define INTDEF(base) (base + 0x42) argument
28 #define BUSDEF(base) (base + 0x44) argument
29 #define RESV0(base) (base + 0x45) argument
30 #define RESV1(base) (base + 0x46) argument
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A Dmyrb.c164 void __iomem *base = cb->io_base; in myrb_qcmd() local
807 void __iomem *base = cb->io_base; in myrb_enable_mmio() local
2666 struct myrb_hba *cb, void __iomem *base) in DAC960_LA_hw_init()
2710 void __iomem *base = cb->io_base; in DAC960_LA_intr_handler() local
2852 DAC960_PG_read_status(void __iomem *base) in DAC960_PG_read_status()
2958 void __iomem *base = cb->io_base; in DAC960_PG_intr_handler() local
3077 DAC960_PD_read_status(void __iomem *base) in DAC960_PD_read_status()
3100 void __iomem *base = cb->io_base; in DAC960_PD_qcmd() local
3154 void __iomem *base = cb->io_base; in DAC960_PD_intr_handler() local
3239 void __iomem *base = cb->io_base; in DAC960_P_qcmd() local
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A Dmyrs.c106 void __iomem *base = cs->io_base; in myrs_qcmd() local
484 void __iomem *base = cs->io_base; in myrs_enable_mmio_mbox() local
2449 static inline void DAC960_GEM_ack_intr(void __iomem *base) in DAC960_GEM_ack_intr()
2537 struct myrs_hba *cs, void __iomem *base) in DAC960_GEM_hw_init()
2576 void __iomem *base = cs->io_base; in DAC960_GEM_intr_handler() local
2672 static inline void DAC960_BA_ack_intr(void __iomem *base) in DAC960_BA_ack_intr()
2756 struct myrs_hba *cs, void __iomem *base) in DAC960_BA_hw_init()
2795 void __iomem *base = cs->io_base; in DAC960_BA_intr_handler() local
2891 static inline void DAC960_LP_ack_intr(void __iomem *base) in DAC960_LP_ack_intr()
2974 struct myrs_hba *cs, void __iomem *base) in DAC960_LP_hw_init()
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/drivers/media/platform/samsung/s5p-jpeg/
A Djpeg-hw-exynos4.c16 void exynos4_jpeg_sw_reset(void __iomem *base) in exynos4_jpeg_sw_reset()
32 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) in exynos4_jpeg_set_enc_dec_mode()
183 unsigned int exynos4_jpeg_get_int_status(void __iomem *base) in exynos4_jpeg_get_int_status()
202 void exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value) in exynos4_jpeg_set_sys_int_enable()
214 void exynos4_jpeg_set_stream_buf_address(void __iomem *base, in exynos4_jpeg_set_stream_buf_address()
220 void exynos4_jpeg_set_stream_size(void __iomem *base, in exynos4_jpeg_set_stream_size()
228 void exynos4_jpeg_set_frame_buf_address(void __iomem *base, in exynos4_jpeg_set_frame_buf_address()
236 void exynos4_jpeg_set_encode_tbl_select(void __iomem *base, in exynos4_jpeg_set_encode_tbl_select()
250 void exynos4_jpeg_set_dec_components(void __iomem *base, int n) in exynos4_jpeg_set_dec_components()
288 unsigned int exynos4_jpeg_get_stream_size(void __iomem *base) in exynos4_jpeg_get_stream_size()
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/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c76 #define RING_REG(base) _MMIO((base) + 0x28) in iterate_generic_mmio() argument
80 #define RING_REG(base) _MMIO((base) + 0x134) in iterate_generic_mmio() argument
84 #define RING_REG(base) _MMIO((base) + 0x6c) in iterate_generic_mmio() argument
98 #define RING_REG(base) _MMIO((base) + 0x29c) in iterate_generic_mmio() argument
787 #define RING_REG(base) _MMIO((base) + 0xd0) in iterate_bdw_plus_mmio() argument
791 #define RING_REG(base) _MMIO((base) + 0x230) in iterate_bdw_plus_mmio() argument
795 #define RING_REG(base) _MMIO((base) + 0x234) in iterate_bdw_plus_mmio() argument
799 #define RING_REG(base) _MMIO((base) + 0x244) in iterate_bdw_plus_mmio() argument
803 #define RING_REG(base) _MMIO((base) + 0x370) in iterate_bdw_plus_mmio() argument
807 #define RING_REG(base) _MMIO((base) + 0x3a0) in iterate_bdw_plus_mmio() argument
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/drivers/media/platform/mediatek/mdp3/
A Dmtk-mdp3-comp.c62 phys_addr_t base = ctx->comp->reg_base; in init_rdma() local
94 phys_addr_t base = ctx->comp->reg_base; in config_rdma_frame() local
284 phys_addr_t base = ctx->comp->reg_base; in config_rdma_subfrm() local
368 phys_addr_t base = ctx->comp->reg_base; in wait_rdma_event() local
396 phys_addr_t base = ctx->comp->reg_base; in init_rsz() local
420 phys_addr_t base = ctx->comp->reg_base; in config_rsz_frame() local
472 phys_addr_t base = ctx->comp->reg_base; in config_rsz_subfrm() local
632 phys_addr_t base = ctx->comp->reg_base; in init_wrot() local
653 phys_addr_t base = ctx->comp->reg_base; in config_wrot_frame() local
773 phys_addr_t base = ctx->comp->reg_base; in config_wrot_subfrm() local
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/drivers/media/platform/mediatek/jpeg/
A Dmtk_jpeg_dec_hw.c219 u32 mtk_jpeg_dec_get_int_status(void __iomem *base) in mtk_jpeg_dec_get_int_status()
248 void mtk_jpeg_dec_start(void __iomem *base) in mtk_jpeg_dec_start()
254 static void mtk_jpeg_dec_soft_reset(void __iomem *base) in mtk_jpeg_dec_soft_reset()
261 static void mtk_jpeg_dec_hard_reset(void __iomem *base) in mtk_jpeg_dec_hard_reset()
267 void mtk_jpeg_dec_reset(void __iomem *base) in mtk_jpeg_dec_reset()
274 static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w, in mtk_jpeg_dec_set_brz_factor()
337 static void mtk_jpeg_dec_set_pause_mcu_idx(void __iomem *base, u32 idx) in mtk_jpeg_dec_set_pause_mcu_idx()
342 static void mtk_jpeg_dec_set_dec_mode(void __iomem *base, u32 mode) in mtk_jpeg_dec_set_dec_mode()
385 static void mtk_jpeg_dec_set_total_mcu(void __iomem *base, u32 num) in mtk_jpeg_dec_set_total_mcu()
390 static void mtk_jpeg_dec_set_comp0_du(void __iomem *base, u32 num) in mtk_jpeg_dec_set_comp0_du()
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/drivers/scsi/pcmcia/
A Dnsp_io.h30 static inline void nsp_write(unsigned int base, in nsp_write()
37 static inline unsigned char nsp_read(unsigned int base, in nsp_read()
75 static inline void nsp_fifo8_read(unsigned int base, in nsp_fifo8_read()
94 static inline void nsp_fifo16_read(unsigned int base, in nsp_fifo16_read()
113 static inline void nsp_fifo32_read(unsigned int base, in nsp_fifo32_read()
132 static inline void nsp_fifo8_write(unsigned int base, in nsp_fifo8_write()
150 static inline void nsp_fifo16_write(unsigned int base, in nsp_fifo16_write()
168 static inline void nsp_fifo32_write(unsigned int base, in nsp_fifo32_write()
178 static inline void nsp_mmio_write(unsigned long base, in nsp_mmio_write()
207 static inline void nsp_mmio_index_write(unsigned long base, in nsp_mmio_index_write()
[all …]
/drivers/i3c/master/mipi-i3c-hci/
A Dext_caps.c24 static int hci_extcap_hardware_id(struct i3c_hci *hci, void __iomem *base) in hci_extcap_hardware_id()
45 static int hci_extcap_master_config(struct i3c_hci *hci, void __iomem *base) in hci_extcap_master_config()
59 static int hci_extcap_multi_bus(struct i3c_hci *hci, void __iomem *base) in hci_extcap_multi_bus()
68 static int hci_extcap_xfer_modes(struct i3c_hci *hci, void __iomem *base) in hci_extcap_xfer_modes()
88 static int hci_extcap_xfer_rates(struct i3c_hci *hci, void __iomem *base) in hci_extcap_xfer_rates()
116 static int hci_extcap_auto_command(struct i3c_hci *hci, void __iomem *base) in hci_extcap_auto_command()
130 static int hci_extcap_debug(struct i3c_hci *hci, void __iomem *base) in hci_extcap_debug()
137 static int hci_extcap_scheduled_cmd(struct i3c_hci *hci, void __iomem *base) in hci_extcap_scheduled_cmd()
157 static int hci_extcap_global_DAT(struct i3c_hci *hci, void __iomem *base) in hci_extcap_global_DAT()
163 static int hci_extcap_multilane(struct i3c_hci *hci, void __iomem *base) in hci_extcap_multilane()
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/drivers/s390/block/
A Ddasd_ioctl.c42 struct dasd_device *base; in dasd_ioctl_enable() local
63 struct dasd_device *base; in dasd_ioctl_disable() local
95 struct dasd_device *base; in dasd_ioctl_quiesce() local
116 struct dasd_device *base; in dasd_ioctl_resume() local
139 struct dasd_device *base; in dasd_ioctl_abortio() local
174 struct dasd_device *base; in dasd_ioctl_allowio() local
195 struct dasd_device *base; in dasd_format() local
233 struct dasd_device *base; in dasd_check_format() local
253 struct dasd_device *base; in dasd_ioctl_format() local
291 struct dasd_device *base; in dasd_ioctl_check_format() local
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/drivers/block/
A Dswim.c88 #define iwm_read(base, reg) in_8(&(base)->reg) argument
211 struct swim __iomem *base; member
428 struct swim __iomem *base = fs->swd->base; in swim_track() local
445 struct swim __iomem *base = fs->swd->base; in floppy_eject() local
461 struct swim __iomem *base = fs->swd->base; in swim_read_sector() local
498 struct swim __iomem *base = fs->swd->base; in floppy_read_sectors() local
585 struct swim __iomem *base = fs->swd->base; in setup_medium() local
614 struct swim __iomem *base = fs->swd->base; in floppy_open() local
674 struct swim __iomem *base = fs->swd->base; in floppy_release() local
751 struct swim __iomem *base = swd->base; in swim_add_floppy() local
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/drivers/gpu/drm/hisilicon/kirin/
A Dkirin_drm_ade.c44 void __iomem *base; member
119 void __iomem *base = ctx->base; in ade_init() local
175 void __iomem *base = ctx->base; in ade_ldi_set_mode() local
249 void __iomem *base = ctx->base; in ade_power_down() local
280 void __iomem *base = ctx->base; in ade_crtc_enable_vblank() local
295 void __iomem *base = ctx->base; in ade_crtc_disable_vblank() local
310 void __iomem *base = ctx->base; in ade_irq_handler() local
328 void __iomem *base = ctx->base; in ade_display_enable() local
508 void __iomem *base = ctx->base; in ade_crtc_atomic_flush() local
716 void __iomem *base = ctx->base; in ade_update_channel() local
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/drivers/clocksource/
A Dtimer-rtl-otto.c58 static inline void rttm_set_counter(void __iomem *base, unsigned int counter) in rttm_set_counter()
63 static inline unsigned int rttm_get_counter(void __iomem *base) in rttm_get_counter()
68 static inline void rttm_set_period(void __iomem *base, unsigned int period) in rttm_set_period()
73 static inline void rttm_disable_timer(void __iomem *base) in rttm_disable_timer()
78 static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor) in rttm_enable_timer()
83 static inline void rttm_ack_irq(void __iomem *base) in rttm_ack_irq()
88 static inline void rttm_enable_irq(void __iomem *base) in rttm_enable_irq()
93 static inline void rttm_disable_irq(void __iomem *base) in rttm_disable_irq()
99 #define RTTM_DEBUG(base) \ argument
115 static void rttm_stop_timer(void __iomem *base) in rttm_stop_timer()
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/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
A Dnv50.c32 nv50_bar_flush(struct nvkm_bar *base) in nv50_bar_flush()
47 nv50_bar_bar1_vmm(struct nvkm_bar *base) in nv50_bar_bar1_vmm()
53 nv50_bar_bar1_wait(struct nvkm_bar *base) in nv50_bar_bar1_wait()
65 nv50_bar_bar1_init(struct nvkm_bar *base) in nv50_bar_bar1_init()
73 nv50_bar_bar2_vmm(struct nvkm_bar *base) in nv50_bar_bar2_vmm()
85 nv50_bar_bar2_init(struct nvkm_bar *base) in nv50_bar_bar2_init()
95 nv50_bar_init(struct nvkm_bar *base) in nv50_bar_init()
106 nv50_bar_oneinit(struct nvkm_bar *base) in nv50_bar_oneinit()
204 nv50_bar_dtor(struct nvkm_bar *base) in nv50_bar_dtor()
/drivers/gpio/
A Dgpio-winbond.c131 unsigned long base; member
142 static int winbond_sio_enter(unsigned long base) in winbond_sio_enter()
157 static void winbond_sio_select_logical(unsigned long base, u8 dev) in winbond_sio_select_logical()
163 static void winbond_sio_leave(unsigned long base) in winbond_sio_leave()
176 static u8 winbond_sio_reg_read(unsigned long base, u8 reg) in winbond_sio_reg_read()
385 unsigned long *base = gpiochip_get_data(gc); in winbond_gpio_get() local
409 unsigned long *base = gpiochip_get_data(gc); in winbond_gpio_direction_in() local
433 unsigned long *base = gpiochip_get_data(gc); in winbond_gpio_direction_out() local
464 unsigned long *base = gpiochip_get_data(gc); in winbond_gpio_set() local
575 static int winbond_gpio_configure(unsigned long base) in winbond_gpio_configure()
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