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Searched defs:div0 (Results 1 – 9 of 9) sorted by relevance

/drivers/clk/uniphier/
A Dclk-uniphier.h110 #define UNIPHIER_CLK_DIV2(parent, div0, div1) \ argument
114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \ argument
118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ argument
122 #define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \ argument
/drivers/clk/samsung/
A Dclk-cpu.c169 unsigned long div0; in exynos_set_safe_div() local
203 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
330 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
A Dclk-cpu.h44 unsigned long div0; member
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
A Dgf100.c278 u32 src0, div0, div1D, div1P = 0; in calc_clk() local
A Dgk104.c292 u32 src0, div0, div1D, div1P = 0; in calc_clk() local
/drivers/clk/x86/
A Dclk-cgu.c395 unsigned int div0, div1, exdiv; in lgm_clk_ddiv_recalc_rate() local
/drivers/i2c/busses/
A Di2c-sprd.c338 u32 div0 = I2C_ADDR_DVD0_CALC(high, low); in sprd_i2c_set_clk() local
/drivers/gpu/drm/i915/display/
A Dintel_dpll_mgr.h215 u32 div0; member
/drivers/clk/nxp/
A Dclk-lpc32xx.c1436 struct clk_hw_proto0 *mux0, *div0, *gate0; in lpc32xx_clk_register() local

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