1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020 - 2025 Intel Corporation 4 */ 5 6 #ifndef IPU7_FW_ISYS_ABI_H 7 #define IPU7_FW_ISYS_ABI_H 8 9 #include "ipu7_fw_common_abi.h" 10 #include "ipu7_fw_isys_abi.h" 11 12 #define IPU_INSYS_MAX_OUTPUT_QUEUES (3U) 13 #define IPU_INSYS_STREAM_ID_MAX (16U) 14 15 #define IPU_INSYS_MAX_INPUT_QUEUES (IPU_INSYS_STREAM_ID_MAX + 1U) 16 #define IPU_INSYS_OUTPUT_FIRST_QUEUE (0U) 17 #define IPU_INSYS_OUTPUT_LAST_QUEUE (IPU_INSYS_MAX_OUTPUT_QUEUES - 1U) 18 #define IPU_INSYS_OUTPUT_MSG_QUEUE (IPU_INSYS_OUTPUT_FIRST_QUEUE) 19 #define IPU_INSYS_OUTPUT_LOG_QUEUE (IPU_INSYS_OUTPUT_FIRST_QUEUE + 1U) 20 #define IPU_INSYS_OUTPUT_RESERVED_QUEUE (IPU_INSYS_OUTPUT_LAST_QUEUE) 21 #define IPU_INSYS_INPUT_FIRST_QUEUE (IPU_INSYS_MAX_OUTPUT_QUEUES) 22 #define IPU_INSYS_INPUT_LAST_QUEUE \ 23 (IPU_INSYS_INPUT_FIRST_QUEUE + IPU_INSYS_MAX_INPUT_QUEUES - 1U) 24 #define IPU_INSYS_INPUT_DEV_QUEUE (IPU_INSYS_INPUT_FIRST_QUEUE) 25 #define IPU_INSYS_INPUT_MSG_QUEUE (IPU_INSYS_INPUT_FIRST_QUEUE + 1U) 26 #define IPU_INSYS_INPUT_MSG_MAX_QUEUE (IPU_INSYS_MAX_INPUT_QUEUES - 1U) 27 28 #define MAX_OPINS_FOR_SINGLE_IPINS (3U) 29 #define DEV_SEND_QUEUE_SIZE (IPU_INSYS_STREAM_ID_MAX) 30 31 #define PIN_PLANES_MAX (4U) 32 33 #define INSYS_MSG_ERR_STREAM_INSUFFICIENT_RESOURCES_INPUT \ 34 INSYS_MSG_ERR_STREAM_INSUFFICIENT_RESOURCES 35 36 typedef u64 ipu7_insys_return_token; 37 38 enum ipu7_insys_resp_type { 39 IPU_INSYS_RESP_TYPE_STREAM_OPEN_DONE = 0, 40 IPU_INSYS_RESP_TYPE_STREAM_START_AND_CAPTURE_ACK = 1, 41 IPU_INSYS_RESP_TYPE_STREAM_CAPTURE_ACK = 2, 42 IPU_INSYS_RESP_TYPE_STREAM_ABORT_ACK = 3, 43 IPU_INSYS_RESP_TYPE_STREAM_FLUSH_ACK = 4, 44 IPU_INSYS_RESP_TYPE_STREAM_CLOSE_ACK = 5, 45 IPU_INSYS_RESP_TYPE_PIN_DATA_READY = 6, 46 IPU_INSYS_RESP_TYPE_FRAME_SOF = 7, 47 IPU_INSYS_RESP_TYPE_FRAME_EOF = 8, 48 IPU_INSYS_RESP_TYPE_STREAM_START_AND_CAPTURE_DONE = 9, 49 IPU_INSYS_RESP_TYPE_STREAM_CAPTURE_DONE = 10, 50 IPU_INSYS_RESP_TYPE_PWM_IRQ = 11, 51 N_IPU_INSYS_RESP_TYPE 52 }; 53 54 enum ipu7_insys_send_type { 55 IPU_INSYS_SEND_TYPE_STREAM_OPEN = 0, 56 IPU_INSYS_SEND_TYPE_STREAM_START_AND_CAPTURE = 1, 57 IPU_INSYS_SEND_TYPE_STREAM_CAPTURE = 2, 58 IPU_INSYS_SEND_TYPE_STREAM_ABORT = 3, 59 IPU_INSYS_SEND_TYPE_STREAM_FLUSH = 4, 60 IPU_INSYS_SEND_TYPE_STREAM_CLOSE = 5, 61 N_IPU_INSYS_SEND_TYPE 62 }; 63 64 enum ipu7_insys_mipi_vc { 65 IPU_INSYS_MIPI_VC_0 = 0, 66 IPU_INSYS_MIPI_VC_1 = 1, 67 IPU_INSYS_MIPI_VC_2 = 2, 68 IPU_INSYS_MIPI_VC_3 = 3, 69 IPU_INSYS_MIPI_VC_4 = 4, 70 IPU_INSYS_MIPI_VC_5 = 5, 71 IPU_INSYS_MIPI_VC_6 = 6, 72 IPU_INSYS_MIPI_VC_7 = 7, 73 IPU_INSYS_MIPI_VC_8 = 8, 74 IPU_INSYS_MIPI_VC_9 = 9, 75 IPU_INSYS_MIPI_VC_10 = 10, 76 IPU_INSYS_MIPI_VC_11 = 11, 77 IPU_INSYS_MIPI_VC_12 = 12, 78 IPU_INSYS_MIPI_VC_13 = 13, 79 IPU_INSYS_MIPI_VC_14 = 14, 80 IPU_INSYS_MIPI_VC_15 = 15, 81 N_IPU_INSYS_MIPI_VC 82 }; 83 84 enum ipu7_insys_mipi_port { 85 IPU_INSYS_MIPI_PORT_0 = 0, 86 IPU_INSYS_MIPI_PORT_1 = 1, 87 IPU_INSYS_MIPI_PORT_2 = 2, 88 IPU_INSYS_MIPI_PORT_3 = 3, 89 IPU_INSYS_MIPI_PORT_4 = 4, 90 IPU_INSYS_MIPI_PORT_5 = 5, 91 NA_IPU_INSYS_MIPI_PORT 92 }; 93 94 enum ipu7_insys_frame_format_type { 95 IPU_INSYS_FRAME_FORMAT_NV11 = 0, 96 IPU_INSYS_FRAME_FORMAT_NV12 = 1, 97 IPU_INSYS_FRAME_FORMAT_NV12_16 = 2, 98 IPU_INSYS_FRAME_FORMAT_NV12_TILEY = 3, 99 IPU_INSYS_FRAME_FORMAT_NV16 = 4, 100 IPU_INSYS_FRAME_FORMAT_NV21 = 5, 101 IPU_INSYS_FRAME_FORMAT_NV61 = 6, 102 IPU_INSYS_FRAME_FORMAT_YV12 = 7, 103 IPU_INSYS_FRAME_FORMAT_YV16 = 8, 104 IPU_INSYS_FRAME_FORMAT_YUV420 = 9, 105 IPU_INSYS_FRAME_FORMAT_YUV420_10 = 10, 106 IPU_INSYS_FRAME_FORMAT_YUV420_12 = 11, 107 IPU_INSYS_FRAME_FORMAT_YUV420_14 = 12, 108 IPU_INSYS_FRAME_FORMAT_YUV420_16 = 13, 109 IPU_INSYS_FRAME_FORMAT_YUV422 = 14, 110 IPU_INSYS_FRAME_FORMAT_YUV422_16 = 15, 111 IPU_INSYS_FRAME_FORMAT_UYVY = 16, 112 IPU_INSYS_FRAME_FORMAT_YUYV = 17, 113 IPU_INSYS_FRAME_FORMAT_YUV444 = 18, 114 IPU_INSYS_FRAME_FORMAT_YUV_LINE = 19, 115 IPU_INSYS_FRAME_FORMAT_RAW8 = 20, 116 IPU_INSYS_FRAME_FORMAT_RAW10 = 21, 117 IPU_INSYS_FRAME_FORMAT_RAW12 = 22, 118 IPU_INSYS_FRAME_FORMAT_RAW14 = 23, 119 IPU_INSYS_FRAME_FORMAT_RAW16 = 24, 120 IPU_INSYS_FRAME_FORMAT_RGB565 = 25, 121 IPU_INSYS_FRAME_FORMAT_PLANAR_RGB888 = 26, 122 IPU_INSYS_FRAME_FORMAT_RGBA888 = 27, 123 IPU_INSYS_FRAME_FORMAT_QPLANE6 = 28, 124 IPU_INSYS_FRAME_FORMAT_BINARY_8 = 29, 125 IPU_INSYS_FRAME_FORMAT_Y_8 = 30, 126 IPU_INSYS_FRAME_FORMAT_ARGB888 = 31, 127 IPU_INSYS_FRAME_FORMAT_BGRA888 = 32, 128 IPU_INSYS_FRAME_FORMAT_ABGR888 = 33, 129 N_IPU_INSYS_FRAME_FORMAT 130 }; 131 132 #define IPU_INSYS_FRAME_FORMAT_RAW (IPU_INSYS_FRAME_FORMAT_RAW16) 133 #define N_IPU_INSYS_MIPI_DATA_TYPE 0x40 134 135 enum ipu7_insys_mipi_dt_rename_mode { 136 IPU_INSYS_MIPI_DT_NO_RENAME = 0, 137 IPU_INSYS_MIPI_DT_RENAMED_MODE = 1, 138 N_IPU_INSYS_MIPI_DT_MODE 139 }; 140 141 #define IPU_INSYS_SEND_MSG_ENABLED 1U 142 #define IPU_INSYS_SEND_MSG_DISABLED 0U 143 144 #define IPU_INSYS_STREAM_SYNC_MSG_SEND_RESP_SOF BIT(0) 145 #define IPU_INSYS_STREAM_SYNC_MSG_SEND_RESP_EOF BIT(1) 146 #define IPU_INSYS_STREAM_SYNC_MSG_SEND_IRQ_SOF BIT(2) 147 #define IPU_INSYS_STREAM_SYNC_MSG_SEND_IRQ_EOF BIT(3) 148 #define IPU_INSYS_STREAM_SYNC_MSG_SEND_RESP_SOF_DISCARDED BIT(4) 149 #define IPU_INSYS_STREAM_SYNC_MSG_SEND_RESP_EOF_DISCARDED BIT(5) 150 #define IPU_INSYS_STREAM_SYNC_MSG_SEND_IRQ_SOF_DISCARDED BIT(6) 151 #define IPU_INSYS_STREAM_SYNC_MSG_SEND_IRQ_EOF_DISCARDED BIT(7) 152 #define IPU_INSYS_STREAM_SYNC_MSG_ENABLE_MSG_SEND_RESP ( \ 153 IPU_INSYS_STREAM_SYNC_MSG_SEND_RESP_SOF | \ 154 IPU_INSYS_STREAM_SYNC_MSG_SEND_RESP_EOF | \ 155 IPU_INSYS_STREAM_SYNC_MSG_SEND_RESP_SOF_DISCARDED | \ 156 IPU_INSYS_STREAM_SYNC_MSG_SEND_RESP_EOF_DISCARDED) 157 #define IPU_INSYS_STREAM_SYNC_MSG_ENABLE_MSG_SEND_IRQ ( \ 158 IPU_INSYS_STREAM_SYNC_MSG_SEND_IRQ_SOF | \ 159 IPU_INSYS_STREAM_SYNC_MSG_SEND_IRQ_EOF | \ 160 IPU_INSYS_STREAM_SYNC_MSG_SEND_IRQ_SOF_DISCARDED | \ 161 IPU_INSYS_STREAM_SYNC_MSG_SEND_IRQ_EOF_DISCARDED) 162 163 #define IPU_INSYS_STREAM_MSG_SEND_RESP_STREAM_OPEN_DONE BIT(0) 164 #define IPU_INSYS_STREAM_MSG_SEND_IRQ_STREAM_OPEN_DONE BIT(1) 165 #define IPU_INSYS_STREAM_MSG_SEND_RESP_STREAM_START_ACK BIT(2) 166 #define IPU_INSYS_STREAM_MSG_SEND_IRQ_STREAM_START_ACK BIT(3) 167 #define IPU_INSYS_STREAM_MSG_SEND_RESP_STREAM_CLOSE_ACK BIT(4) 168 #define IPU_INSYS_STREAM_MSG_SEND_IRQ_STREAM_CLOSE_ACK BIT(5) 169 #define IPU_INSYS_STREAM_MSG_SEND_RESP_STREAM_FLUSH_ACK BIT(6) 170 #define IPU_INSYS_STREAM_MSG_SEND_IRQ_STREAM_FLUSH_ACK BIT(7) 171 #define IPU_INSYS_STREAM_MSG_SEND_RESP_STREAM_ABORT_ACK BIT(8) 172 #define IPU_INSYS_STREAM_MSG_SEND_IRQ_STREAM_ABORT_ACK BIT(9) 173 #define IPU_INSYS_STREAM_ENABLE_MSG_SEND_RESP ( \ 174 IPU_INSYS_STREAM_MSG_SEND_RESP_STREAM_OPEN_DONE | \ 175 IPU_INSYS_STREAM_MSG_SEND_RESP_STREAM_START_ACK | \ 176 IPU_INSYS_STREAM_MSG_SEND_RESP_STREAM_CLOSE_ACK | \ 177 IPU_INSYS_STREAM_MSG_SEND_RESP_STREAM_FLUSH_ACK | \ 178 IPU_INSYS_STREAM_MSG_SEND_RESP_STREAM_ABORT_ACK) 179 #define IPU_INSYS_STREAM_ENABLE_MSG_SEND_IRQ ( \ 180 IPU_INSYS_STREAM_MSG_SEND_IRQ_STREAM_OPEN_DONE | \ 181 IPU_INSYS_STREAM_MSG_SEND_IRQ_STREAM_START_ACK | \ 182 IPU_INSYS_STREAM_MSG_SEND_IRQ_STREAM_CLOSE_ACK | \ 183 IPU_INSYS_STREAM_MSG_SEND_IRQ_STREAM_FLUSH_ACK | \ 184 IPU_INSYS_STREAM_MSG_SEND_IRQ_STREAM_ABORT_ACK) 185 186 #define IPU_INSYS_FRAME_MSG_SEND_RESP_CAPTURE_ACK BIT(0) 187 #define IPU_INSYS_FRAME_MSG_SEND_IRQ_CAPTURE_ACK BIT(1) 188 #define IPU_INSYS_FRAME_MSG_SEND_RESP_CAPTURE_DONE BIT(2) 189 #define IPU_INSYS_FRAME_MSG_SEND_IRQ_CAPTURE_DONE BIT(3) 190 #define IPU_INSYS_FRAME_MSG_SEND_RESP_PIN_DATA_READY BIT(4) 191 #define IPU_INSYS_FRAME_MSG_SEND_IRQ_PIN_DATA_READY BIT(5) 192 #define IPU_INSYS_FRAME_ENABLE_MSG_SEND_RESP ( \ 193 IPU_INSYS_FRAME_MSG_SEND_RESP_CAPTURE_ACK | \ 194 IPU_INSYS_FRAME_MSG_SEND_RESP_CAPTURE_DONE | \ 195 IPU_INSYS_FRAME_MSG_SEND_RESP_PIN_DATA_READY) 196 #define IPU_INSYS_FRAME_ENABLE_MSG_SEND_IRQ ( \ 197 IPU_INSYS_FRAME_MSG_SEND_IRQ_CAPTURE_ACK | \ 198 IPU_INSYS_FRAME_MSG_SEND_IRQ_CAPTURE_DONE | \ 199 IPU_INSYS_FRAME_MSG_SEND_IRQ_PIN_DATA_READY) 200 201 enum ipu7_insys_output_link_dest { 202 IPU_INSYS_OUTPUT_LINK_DEST_MEM = 0, 203 IPU_INSYS_OUTPUT_LINK_DEST_PSYS = 1, 204 IPU_INSYS_OUTPUT_LINK_DEST_IPU_EXTERNAL = 2 205 }; 206 207 enum ipu7_insys_dpcm_type { 208 IPU_INSYS_DPCM_TYPE_DISABLED = 0, 209 IPU_INSYS_DPCM_TYPE_10_8_10 = 1, 210 IPU_INSYS_DPCM_TYPE_12_8_12 = 2, 211 IPU_INSYS_DPCM_TYPE_12_10_12 = 3, 212 N_IPU_INSYS_DPCM_TYPE 213 }; 214 215 enum ipu7_insys_dpcm_predictor { 216 IPU_INSYS_DPCM_PREDICTOR_1 = 0, 217 IPU_INSYS_DPCM_PREDICTOR_2 = 1, 218 N_IPU_INSYS_DPCM_PREDICTOR 219 }; 220 221 enum ipu7_insys_send_queue_token_flag { 222 IPU_INSYS_SEND_QUEUE_TOKEN_FLAG_NONE = 0, 223 IPU_INSYS_SEND_QUEUE_TOKEN_FLAG_FLUSH_FORCE = 1 224 }; 225 226 #pragma pack(push, 1) 227 struct ipu7_insys_resolution { 228 u32 width; 229 u32 height; 230 }; 231 232 struct ipu7_insys_capture_output_pin_payload { 233 u64 user_token; 234 ia_gofo_addr_t addr; 235 u8 pad[4]; 236 }; 237 238 struct ipu7_insys_output_link { 239 u32 buffer_lines; 240 u16 foreign_key; 241 u16 granularity_pointer_update; 242 u8 msg_link_streaming_mode; 243 u8 pbk_id; 244 u8 pbk_slot_id; 245 u8 dest; 246 u8 use_sw_managed; 247 u8 is_snoop; 248 u8 pad[2]; 249 }; 250 251 struct ipu7_insys_output_cropping { 252 u16 line_top; 253 u16 line_bottom; 254 }; 255 256 struct ipu7_insys_output_dpcm { 257 u8 enable; 258 u8 type; 259 u8 predictor; 260 u8 pad; 261 }; 262 263 struct ipu7_insys_output_pin { 264 struct ipu7_insys_output_link link; 265 struct ipu7_insys_output_cropping crop; 266 struct ipu7_insys_output_dpcm dpcm; 267 u32 stride; 268 u16 ft; 269 u8 send_irq; 270 u8 input_pin_id; 271 u8 early_ack_en; 272 u8 pad[3]; 273 }; 274 275 struct ipu7_insys_input_pin { 276 struct ipu7_insys_resolution input_res; 277 u16 sync_msg_map; 278 u8 dt; 279 u8 disable_mipi_unpacking; 280 u8 dt_rename_mode; 281 u8 mapped_dt; 282 u8 pad[2]; 283 }; 284 285 struct ipu7_insys_stream_cfg { 286 struct ipu7_insys_input_pin input_pins[4]; 287 struct ipu7_insys_output_pin output_pins[4]; 288 u16 stream_msg_map; 289 u8 port_id; 290 u8 vc; 291 u8 nof_input_pins; 292 u8 nof_output_pins; 293 u8 pad[2]; 294 }; 295 296 struct ipu7_insys_buffset { 297 struct ipu7_insys_capture_output_pin_payload output_pins[4]; 298 u8 capture_msg_map; 299 u8 frame_id; 300 u8 skip_frame; 301 u8 pad[5]; 302 }; 303 304 struct ipu7_insys_resp { 305 u64 buf_id; 306 struct ipu7_insys_capture_output_pin_payload pin; 307 struct ia_gofo_msg_err error_info; 308 u32 timestamp[2]; 309 u8 type; 310 u8 msg_link_streaming_mode; 311 u8 stream_id; 312 u8 pin_id; 313 u8 frame_id; 314 u8 skip_frame; 315 u8 pad[2]; 316 }; 317 318 struct ipu7_insys_resp_queue_token { 319 struct ipu7_insys_resp resp_info; 320 }; 321 322 struct ipu7_insys_send_queue_token { 323 u64 buf_handle; 324 ia_gofo_addr_t addr; 325 u16 stream_id; 326 u8 send_type; 327 u8 flag; 328 }; 329 330 #pragma pack(pop) 331 332 enum insys_msg_err_stream { 333 INSYS_MSG_ERR_STREAM_OK = IA_GOFO_MSG_ERR_OK, 334 INSYS_MSG_ERR_STREAM_STREAM_ID = 1, 335 INSYS_MSG_ERR_STREAM_MAX_OPINS = 2, 336 INSYS_MSG_ERR_STREAM_MAX_IPINS = 3, 337 INSYS_MSG_ERR_STREAM_STREAM_MESSAGES_MAP = 4, 338 INSYS_MSG_ERR_STREAM_SYNC_MESSAGES_MAP = 5, 339 INSYS_MSG_ERR_STREAM_SENSOR_TYPE = 6, 340 INSYS_MSG_ERR_STREAM_FOREIGN_KEY = 7, 341 INSYS_MSG_ERR_STREAM_STREAMING_MODE = 8, 342 INSYS_MSG_ERR_STREAM_DPCM_EN = 9, 343 INSYS_MSG_ERR_STREAM_DPCM_TYPE = 10, 344 INSYS_MSG_ERR_STREAM_DPCM_PREDICTOR = 11, 345 INSYS_MSG_ERR_STREAM_GRANULARITY_POINTER_UPDATE = 12, 346 INSYS_MSG_ERR_STREAM_MPF_LUT_ENTRY_RESOURCES_BUSY = 13, 347 INSYS_MSG_ERR_STREAM_MPF_DEV_ID = 14, 348 INSYS_MSG_ERR_STREAM_BUFFER_LINES = 15, 349 INSYS_MSG_ERR_STREAM_IPIN_ID = 16, 350 INSYS_MSG_ERR_STREAM_DATA_TYPE = 17, 351 INSYS_MSG_ERR_STREAM_STREAMING_PROTOCOL_STATE = 18, 352 INSYS_MSG_ERR_STREAM_SYSCOM_FLUSH = 19, 353 INSYS_MSG_ERR_STREAM_MIPI_VC = 20, 354 INSYS_MSG_ERR_STREAM_STREAM_SRC = 21, 355 INSYS_MSG_ERR_STREAM_PBK_ID = 22, 356 INSYS_MSG_ERR_STREAM_CMD_QUEUE_DEALLOCATE = 23, 357 INSYS_MSG_ERR_STREAM_INSUFFICIENT_RESOURCES = 24, 358 INSYS_MSG_ERR_STREAM_IPIN_CONFIGURATION = 25, 359 INSYS_MSG_ERR_STREAM_INVALID_STATE = 26, 360 INSYS_MSG_ERR_STREAM_SW_MANAGED = 27, 361 INSYS_MSG_ERR_STREAM_PBK_SLOT_ID = 28, 362 INSYS_MSG_ERR_STREAM_FLUSH_TIMEOUT = 29, 363 INSYS_MSG_ERR_STREAM_IPIN_WIDTH = 30, 364 INSYS_MSG_ERR_STREAM_IPIN_HEIGHT = 31, 365 INSYS_MSG_ERR_STREAM_OUTPUT_PIN_EARLY_ACK_EN = 32, 366 INSYS_MSG_ERR_STREAM_INCONSISTENT_PARAMS = 33, 367 INSYS_MSG_ERR_STREAM_PLANE_COUNT = 34, 368 INSYS_MSG_ERR_STREAM_FRAME_FORMAT_TYPE = 35, 369 INSYS_MSG_ERR_STREAM_INSUFFICIENT_RESOURCES_OUTPUT = 36, 370 INSYS_MSG_ERR_STREAM_WIDTH_OUTPUT_SIZE = 37, 371 INSYS_MSG_ERR_STREAM_CLOSED = 38, 372 INSYS_MSG_ERR_STREAM_N 373 }; 374 375 enum insys_msg_err_capture { 376 INSYS_MSG_ERR_CAPTURE_OK = IA_GOFO_MSG_ERR_OK, 377 INSYS_MSG_ERR_CAPTURE_STREAM_ID = 1, 378 INSYS_MSG_ERR_CAPTURE_PAYLOAD_PTR = 2, 379 INSYS_MSG_ERR_CAPTURE_MEM_SLOT = 3, 380 INSYS_MSG_ERR_CAPTURE_STREAMING_MODE = 4, 381 INSYS_MSG_ERR_CAPTURE_AVAILABLE_CMD_SLOT = 5, 382 INSYS_MSG_ERR_CAPTURE_CONSUMED_CMD_SLOT = 6, 383 INSYS_MSG_ERR_CAPTURE_CMD_SLOT_PAYLOAD_PTR = 7, 384 INSYS_MSG_ERR_CAPTURE_CMD_PREPARE = 8, 385 INSYS_MSG_ERR_CAPTURE_OUTPUT_PIN = 9, 386 INSYS_MSG_ERR_CAPTURE_SYNC_FRAME_DROP = 10, 387 INSYS_MSG_ERR_CAPTURE_FRAME_MESSAGES_MAP = 11, 388 INSYS_MSG_ERR_CAPTURE_TIMEOUT = 12, 389 INSYS_MSG_ERR_CAPTURE_INVALID_STREAM_STATE = 13, 390 INSYS_MSG_ERR_CAPTURE_HW_ERR_MULTIBIT_PH_ERROR_DETECTED = 14, 391 INSYS_MSG_ERR_CAPTURE_HW_ERR_PAYLOAD_CRC_ERROR = 15, 392 INSYS_MSG_ERR_CAPTURE_HW_ERR_INPUT_DATA_LOSS_ELASTIC_FIFO_OVFL = 16, 393 INSYS_MSG_ERR_CAPTURE_HW_ERR_PIXEL_BUFFER_OVERFLOW = 17, 394 INSYS_MSG_ERR_CAPTURE_HW_ERR_BAD_FRAME_DIM = 18, 395 INSYS_MSG_ERR_CAPTURE_HW_ERR_PHY_SYNC_ERR = 19, 396 INSYS_MSG_ERR_CAPTURE_HW_ERR_SECURE_TOUCH = 20, 397 INSYS_MSG_ERR_CAPTURE_HW_ERR_MASTER_SLAVE_SYNC_ERR = 21, 398 INSYS_MSG_ERR_CAPTURE_FRAME_SKIP_ERR = 22, 399 INSYS_MSG_ERR_CAPTURE_FE_INPUT_FIFO_OVERFLOW_ERR = 23, 400 INSYS_MSG_ERR_CAPTURE_CMD_SUBMIT_TO_HW = 24, 401 INSYS_MSG_ERR_CAPTURE_N 402 }; 403 404 enum insys_msg_err_groups { 405 INSYS_MSG_ERR_GROUP_RESERVED = IA_GOFO_MSG_ERR_GROUP_RESERVED, 406 INSYS_MSG_ERR_GROUP_GENERAL = IA_GOFO_MSG_ERR_GROUP_GENERAL, 407 INSYS_MSG_ERR_GROUP_STREAM = 2, 408 INSYS_MSG_ERR_GROUP_CAPTURE = 3, 409 INSYS_MSG_ERR_GROUP_N, 410 }; 411 412 #endif 413