Home
last modified time | relevance | path

Searched defs:layer (Results 1 – 25 of 56) sorted by relevance

123

/drivers/net/ethernet/microchip/sparx5/
A Dsparx5_qos.c107 static u32 sparx5_lg_get_next(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_get_next()
117 static u32 sparx5_lg_get_last(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_last()
132 static bool sparx5_lg_is_last(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_is_last()
158 static void sparx5_lg_enable(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_enable()
169 static int sparx5_lg_get_group_by_index(struct sparx5 *sparx5, u32 layer, in sparx5_lg_get_group_by_index()
198 static int sparx5_lg_get_group_by_rate(u32 layer, u32 rate, u32 *group) in sparx5_lg_get_group_by_rate()
331 const struct sparx5_shaper *sh, u32 layer, in sparx5_shaper_conf_set()
370 u32 layer = is_sparx5(port->sparx5) ? 2 : 1; in sparx5_dwrr_conf_set() local
395 struct sparx5_layer *layer; in sparx5_leak_groups_init() local
498 u32 layer, u32 idx) in sparx5_tc_tbf_add()
[all …]
A Dsparx5_tc.c64 u32 portno, u32 *layer, u32 *idx) in sparx5_tc_get_layer_and_idx()
91 u32 layer, se_idx; in sparx5_tc_setup_qdisc_tbf() local
/drivers/gpu/drm/xlnx/
A Dzynqmp_disp.c427 struct zynqmp_disp_layer *layer, in zynqmp_disp_avbuf_set_format()
572 struct zynqmp_disp_layer *layer) in zynqmp_disp_avbuf_enable_video()
602 struct zynqmp_disp_layer *layer) in zynqmp_disp_avbuf_disable_video()
778 struct zynqmp_disp_layer *layer, in zynqmp_disp_blend_layer_set_csc()
824 struct zynqmp_disp_layer *layer) in zynqmp_disp_blend_layer_enable()
856 struct zynqmp_disp_layer *layer) in zynqmp_disp_blend_layer_disable()
1109 int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer, in zynqmp_disp_layer_update()
1161 struct zynqmp_disp_layer *layer) in zynqmp_disp_layer_release_dma()
1202 struct zynqmp_disp_layer *layer) in zynqmp_disp_layer_request_dma()
1256 struct zynqmp_disp_layer *layer = &disp->layers[i]; in zynqmp_disp_create_layers() local
[all …]
A Dzynqmp_kms.c81 struct zynqmp_disp_layer *layer = dpsub->layers[plane->index]; in zynqmp_dpsub_plane_atomic_disable() local
99 struct zynqmp_disp_layer *layer = dpsub->layers[plane->index]; in zynqmp_dpsub_plane_atomic_update() local
154 struct zynqmp_disp_layer *layer = dpsub->layers[i]; in zynqmp_dpsub_create_planes() local
/drivers/gpu/drm/logicvc/
A Dlogicvc_layer.c87 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_check() local
140 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_update() local
237 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_disable() local
260 struct logicvc_layer *layer, in logicvc_layer_buffer_find_setup()
383 struct logicvc_layer *layer) in logicvc_layer_config_parse()
435 struct logicvc_layer *layer; in logicvc_layer_get_from_index() local
447 struct logicvc_layer *layer; in logicvc_layer_get_from_type() local
466 struct logicvc_layer *layer = NULL; in logicvc_layer_init() local
558 struct logicvc_layer *layer) in logicvc_layer_fini()
569 struct logicvc_layer *layer; in logicvc_layers_attach_crtc() local
[all …]
/drivers/gpu/drm/sun4i/
A Dsun8i_ui_layer.h17 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \ argument
19 #define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \ argument
21 #define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \ argument
23 #define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \ argument
25 #define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \ argument
27 #define SUN8I_MIXER_CHAN_UI_LAYER_BOT_LADDR(base, layer) \ argument
29 #define SUN8I_MIXER_CHAN_UI_LAYER_FCOLOR(base, layer) \ argument
A Dsun8i_vi_layer.h11 #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \ argument
13 #define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \ argument
15 #define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \ argument
17 #define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \ argument
19 #define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \ argument
A Dsun4i_backend.c84 int layer, bool enable) in sun4i_backend_layer_enable()
172 int layer, struct drm_plane *plane) in sun4i_backend_update_layer_coord()
196 int layer, struct drm_plane *plane) in sun4i_backend_update_yuv_format()
253 int layer, struct drm_plane *plane) in sun4i_backend_update_layer_formats()
290 int layer, uint32_t fmt) in sun4i_backend_update_layer_frontend()
329 int layer, struct drm_plane *plane) in sun4i_backend_update_layer_buffer()
366 int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer, in sun4i_backend_update_layer_zpos()
386 int layer) in sun4i_backend_cleanup_layer()
410 struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane); in sun4i_backend_plane_uses_frontend() local
A Dsun4i_layer.c69 struct sun4i_layer *layer = plane_to_sun4i_layer(plane); in sun4i_backend_layer_atomic_disable() local
89 struct sun4i_layer *layer = plane_to_sun4i_layer(plane); in sun4i_backend_layer_atomic_update() local
117 struct sun4i_layer *layer = plane_to_sun4i_layer(plane); in sun4i_layer_format_mod_supported() local
198 struct sun4i_layer *layer; in sun4i_layer_init_one() local
249 struct sun4i_layer *layer; in sun4i_layers_init() local
A Dsun8i_csc.c143 static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, in sun8i_de3_ccsc_set_coefficients()
193 static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable) in sun8i_de3_ccsc_enable()
208 void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, in sun8i_csc_set_ccsc_coefficients()
227 void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable) in sun8i_csc_enable_ccsc()
A Dsun8i_mixer.c253 static void sun8i_layer_enable(struct sun8i_layer *layer, bool enable) in sun8i_layer_enable()
285 struct sun8i_layer *layer = plane_to_sun8i_layer(plane); in sun8i_mixer_commit() local
340 struct sun8i_layer *layer; in sun8i_layers_init() local
353 struct sun8i_layer *layer; in sun8i_layers_init() local
A Dsun8i_ui_layer.c201 struct sun8i_layer *layer = plane_to_sun8i_layer(plane); in sun8i_ui_layer_atomic_check() local
234 struct sun8i_layer *layer = plane_to_sun8i_layer(plane); in sun8i_ui_layer_atomic_update() local
299 struct sun8i_layer *layer; in sun8i_ui_layer_init_one() local
A Dsun8i_ui_scaler.c130 void sun8i_ui_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable) in sun8i_ui_scaler_enable()
148 void sun8i_ui_scaler_setup(struct sun8i_mixer *mixer, int layer, in sun8i_ui_scaler_setup()
A Dsun8i_vi_layer.c322 struct sun8i_layer *layer = plane_to_sun8i_layer(plane); in sun8i_vi_layer_atomic_check() local
354 struct sun8i_layer *layer = plane_to_sun8i_layer(plane); in sun8i_vi_layer_atomic_update() local
480 struct sun8i_layer *layer; in sun8i_vi_layer_init_one() local
A Dsun8i_vi_scaler.c912 void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable) in sun8i_vi_scaler_enable()
928 void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer, in sun8i_vi_scaler_setup()
/drivers/media/dvb-frontends/
A Dmb86a20s.c377 unsigned layer) in mb86a20s_get_modulation()
409 unsigned layer) in mb86a20s_get_fec()
444 unsigned layer) in mb86a20s_get_interleaving()
470 unsigned layer) in mb86a20s_get_segment_count()
543 u32 layer) in isdbt_layer_min_bitrate()
793 unsigned layer, in mb86a20s_get_pre_ber()
926 unsigned layer, in mb86a20s_get_post_ber()
1054 unsigned layer, in mb86a20s_get_blk_error()
1427 int rc, val, layer; in mb86a20s_get_blk_error_layer_CNR() local
1528 int layer; in mb86a20s_stats_not_ready() local
[all …]
/drivers/gpu/drm/atmel-hlcdc/
A Datmel_hlcdc_dc.h322 struct atmel_hlcdc_layer layer; member
332 atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer) in atmel_hlcdc_layer_to_plane()
435 static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer, in atmel_hlcdc_layer_write_reg()
441 static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer, in atmel_hlcdc_layer_read_reg()
451 static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer, in atmel_hlcdc_layer_write_cfg()
459 static inline u32 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer *layer, in atmel_hlcdc_layer_read_cfg()
467 static inline void atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer *layer, in atmel_hlcdc_layer_write_clut()
475 static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer, in atmel_hlcdc_layer_init()
/drivers/gpu/drm/arm/display/komeda/
A Dkomeda_plane.c78 struct komeda_layer *layer = kplane->layer; in komeda_plane_atomic_check() local
241 struct komeda_layer *layer) in komeda_plane_add()
A Dkomeda_pipeline_state.c283 komeda_layer_check_cfg(struct komeda_layer *layer, in komeda_layer_check_cfg()
338 komeda_layer_validate(struct komeda_layer *layer, in komeda_layer_validate()
839 void komeda_complete_data_flow_cfg(struct komeda_layer *layer, in komeda_complete_data_flow_cfg()
882 int komeda_build_layer_data_flow(struct komeda_layer *layer, in komeda_build_layer_data_flow()
A Dkomeda_kms.h33 struct komeda_layer *layer; member
/drivers/gpu/drm/tidss/
A Dtidss_crtc.c127 int layer; in tidss_crtc_position_planes() local
274 for (u32 layer = 0; layer < tidss->feat->num_vids; layer++) in tidss_crtc_atomic_disable() local
/drivers/gpu/drm/vmwgfx/
A Dvmw_surface_cache.h369 u32 mip_level, u32 layer) in vmw_surface_subres()
445 u32 layer; in vmw_surface_get_loc() local
/drivers/infiniband/sw/siw/
A Diwarp.h183 __be32 layer : 4; member
197 __be32 layer : 4; member
222 u8 layer) in __rdmap_term_set_layer()
/drivers/edac/
A Dedac_mc.c259 int layer; in edac_mc_alloc_dimms() local
341 struct edac_mc_layer *layer; in edac_mc_alloc() local
/drivers/gpu/drm/arm/
A Dmalidp_drv.h54 const struct malidp_layer *layer; member

Completed in 57 milliseconds

123