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Searched defs:n (Results 1 – 25 of 2222) sorted by relevance

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/drivers/media/pci/solo6x10/
A Dsolo6x10-regs.h49 #define SOLO_VCLK_SELECT(n) ((n)<<20) argument
61 #define SOLO_IRQ_P2M(n) BIT((n) + 17) argument
73 #define SOLO_IRQ_UART(n) BIT((n) + 4) argument
126 #define SOLO_P2M_REPEAT(n) ((n)<<10) argument
177 #define SOLO_VI_H_START(n) ((n)<<21) argument
178 #define SOLO_VI_V_START(n) ((n)<<11) argument
179 #define SOLO_VI_V_STOP(n) ((n)<<0) argument
267 #define SOLO_VO_H_STOP(n) ((n)<<0) argument
272 #define SOLO_VO_V_STOP(n) ((n)<<0) argument
278 #define SOLO_VO_H_LEN(n) ((n)<<11) argument
[all …]
A Dsolo6x10-tw28.h19 #define TW_CHIP_OFFSET_ADDR(n) (TW_BASE_ADDR + (n)) argument
23 #define TW_HUE_ADDR(n) (0x07 | ((n) << 4)) argument
24 #define TW_SATURATION_ADDR(n) (0x08 | ((n) << 4)) argument
25 #define TW_CONTRAST_ADDR(n) (0x09 | ((n) << 4)) argument
26 #define TW_BRIGHTNESS_ADDR(n) (0x0a | ((n) << 4)) argument
32 #define TW286x_HUE_ADDR(n) (0x06 | ((n) << 4)) argument
33 #define TW286x_SATURATIONU_ADDR(n) (0x04 | ((n) << 4)) argument
34 #define TW286x_SATURATIONV_ADDR(n) (0x05 | ((n) << 4)) argument
35 #define TW286x_CONTRAST_ADDR(n) (0x02 | ((n) << 4)) argument
36 #define TW286x_BRIGHTNESS_ADDR(n) (0x01 | ((n) << 4)) argument
[all …]
/drivers/phy/allwinner/
A Dphy-sun6i-mipi-dphy.c38 #define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n) ((n) & 0xff) argument
44 #define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n) ((n) & 0xff) argument
47 #define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n) ((n) & 0xff) argument
53 #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff) argument
80 #define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12) argument
83 #define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2) argument
111 #define SUN6I_DPHY_ANA4_REG_IB(n) (((n) & 3) << 25) argument
121 #define SUN6I_DPHY_ANA4_REG_TXPUSD(n) ((n) & 3) argument
139 #define SUN50I_DPHY_PLL_REG0_M1(n) ((n) & 0xf) argument
158 #define SUN50I_DPHY_PLL_REG2_FRAC(n) ((n) & 0xfff) argument
[all …]
/drivers/staging/media/starfive/camss/
A Dstf-isp.h32 #define CSI_INTS(n) ((n) << 16) argument
56 #define SMY13(n) ((n) << 14) argument
57 #define SMY12(n) ((n) << 12) argument
58 #define SMY11(n) ((n) << 10) argument
59 #define SMY10(n) ((n) << 8) argument
60 #define SMY3(n) ((n) << 6) argument
61 #define SMY2(n) ((n) << 4) argument
62 #define SMY1(n) ((n) << 2) argument
63 #define SMY0(n) ((n) << 0) argument
383 #define TH(n) ((n) << 8) argument
[all …]
/drivers/gpu/drm/panel/
A Dpanel-sitronix-st7789v.c23 #define ST7789V_RAMCTRL_EPF(n) (((n) & 3) << 4) argument
27 #define ST7789V_RGBCTRL_RCM(n) (((n) & 3) << 5) argument
32 #define ST7789V_RGBCTRL_VBP(n) ((n) & 0x7f) argument
33 #define ST7789V_RGBCTRL_HBP(n) ((n) & 0x1f) argument
37 #define ST7789V_PORCTRL_IDLE_FP(n) ((n) & 0xf) argument
43 #define ST7789V_GCTRL_VGLS(n) ((n) & 7) argument
65 #define ST7789V_PWCTRL1_VDS(n) ((n) & 3) argument
70 #define ST7789V_PVGAMCTRL_VP0(n) ((n) & 0xf) argument
77 #define ST7789V_PVGAMCTRL_VP27(n) ((n) & 7) argument
90 #define ST7789V_NVGAMCTRL_VN0(n) ((n) & 0xf) argument
[all …]
/drivers/media/platform/nxp/imx8-isi/
A Dimx8-isi-regs.h17 #define CHNL_CTRL_CHAIN_BUF(n) ((n) << 25) argument
22 #define CHNL_CTRL_BLANK_PXL(n) ((n) << 16) argument
24 #define CHNL_CTRL_MIPI_VC_ID(n) ((n) << 6) argument
26 #define CHNL_CTRL_SRC_TYPE(n) ((n) << 4) argument
30 #define CHNL_CTRL_SRC_INPUT(n) ((n) << 0) argument
35 #define CHNL_IMG_CTRL_FORMAT(n) ((n) << 24) argument
195 #define CHNL_CROP_ULC_X(n) ((n) << 16) argument
197 #define CHNL_CROP_ULC_Y(n) ((n) << 0) argument
202 #define CHNL_CROP_LRC_X(n) ((n) << 16) argument
204 #define CHNL_CROP_LRC_Y(n) ((n) << 0) argument
[all …]
/drivers/phy/marvell/
A Dphy-mvebu-cp110-comphy.c21 #define MVEBU_COMPHY_SERDES_CFG0(n) (0x0 + (n) * 0x1000) argument
23 #define MVEBU_COMPHY_SERDES_CFG0_GEN_RX(n) ((n) << 3) argument
24 #define MVEBU_COMPHY_SERDES_CFG0_GEN_TX(n) ((n) << 7) argument
42 #define MVEBU_COMPHY_PWRPLL_PHY_MODE(n) ((n) << 5) argument
44 #define MVEBU_COMPHY_IMP_CAL_TX_EXT(n) ((n) << 10) argument
48 #define MVEBU_COMPHY_COEF(n) (0x828 + (n) * 0x1000) argument
52 #define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1) argument
78 #define MVEBU_SP_CALIB(n) (0x96c + (n) * 0x1000) argument
79 #define MVEBU_SP_CALIB_SAMPLER(n) ((n) << 8) argument
106 #define MVEBU_COMPHY_GEN1_S5_ICP(n) ((n) << 0) argument
[all …]
/drivers/media/platform/qcom/camss/
A Dcamss-vfe-480.c22 static inline int reg_update_rdi(struct vfe_device *vfe, int n) in reg_update_rdi()
31 #define VFE_IRQ_MASK(n) ((vfe_is_lite(vfe) ? 0x28 : 0x3c) + (n) * 4) argument
34 #define VFE_IRQ_CLEAR(n) ((vfe_is_lite(vfe) ? 0x34 : 0x48) + (n) * 4) argument
35 #define VFE_IRQ_STATUS(n) ((vfe_is_lite(vfe) ? 0x40 : 0x54) + (n) * 4) argument
44 #define VFE_BUS_IRQ_MASK(n) (BUS_REG_BASE + 0x18 + (n) * 4) argument
57 #define VFE_BUS_IRQ_CLEAR(n) (BUS_REG_BASE + 0x20 + (n) * 4) argument
58 #define VFE_BUS_IRQ_STATUS(n) (BUS_REG_BASE + 0x28 + (n) * 4) argument
61 #define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) argument
66 #define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100) argument
88 #define RDI_WM(n) ((vfe_is_lite(vfe) ? 0 : 23) + (n)) argument
[all …]
A Dcamss-vfe-17x.c48 #define MASK_0_RDI_REG_UPDATE(n) BIT((n) + 5) argument
58 #define MASK_1_RDI_SOF(n) BIT((n) + 29) argument
65 #define STATUS_0_RDI_REG_UPDATE(n) BIT((n) + 5) argument
73 #define STATUS_1_RDI_SOF(n) BIT((n) + 27) argument
96 #define REG_UPDATE_RDI(n) BIT(1 + (n)) argument
98 #define VFE_BUS_IRQ_MASK(n) (0x2044 + (n) * 4) argument
99 #define VFE_BUS_IRQ_CLEAR(n) (0x2050 + (n) * 4) argument
113 #define STATUS0_COMP_BUF_DONE(n) BIT((n) + 5) argument
119 #define STATUS1_WM_CLIENT_BUF_DONE(n) BIT(n) argument
127 #define STATUS2_DUAL_COMP_BUF_DONE(n) BIT(n) argument
[all …]
A Dcamss-vfe-780.c22 #define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) argument
26 #define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100) argument
27 #define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100) argument
28 #define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100) argument
30 #define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100) argument
32 #define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100) argument
34 #define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100) argument
36 #define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100) argument
37 #define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100) argument
39 #define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100) argument
[all …]
A Dcamss-csiphy-3ph-1-0.c18 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) argument
20 #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n)) argument
22 #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n)) argument
23 #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n)) argument
26 #define CSIPHY_3PH_LNn_CFG5(n) (0x010 + 0x100 * (n)) argument
29 #define CSIPHY_3PH_LNn_TEST_IMP(n) (0x01c + 0x100 * (n)) argument
31 #define CSIPHY_3PH_LNn_MISC1(n) (0x028 + 0x100 * (n)) argument
33 #define CSIPHY_3PH_LNn_CFG6(n) (0x02c + 0x100 * (n)) argument
35 #define CSIPHY_3PH_LNn_CFG7(n) (0x030 + 0x100 * (n)) argument
37 #define CSIPHY_3PH_LNn_CFG8(n) (0x034 + 0x100 * (n)) argument
[all …]
/drivers/gpu/drm/omapdrm/dss/
A Ddispc.h37 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ argument
39 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \ argument
41 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \ argument
43 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \ argument
45 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \ argument
47 #define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \ argument
57 #define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \ argument
65 #define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \ argument
67 #define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \ argument
71 #define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \ argument
[all …]
/drivers/video/fbdev/omap2/omapfb/dss/
A Ddispc.h34 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ argument
36 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \ argument
38 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \ argument
40 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \ argument
42 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \ argument
44 #define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \ argument
54 #define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \ argument
62 #define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \ argument
64 #define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \ argument
68 #define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \ argument
[all …]
/drivers/gpu/drm/exynos/
A Dregs-decon5433.h12 #define DECON_WINCONx(n) (0x0020 + ((n) * 4)) argument
13 #define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4)) argument
15 #define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20)) argument
16 #define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20)) argument
17 #define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20)) argument
18 #define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20)) argument
33 #define DECON_WINxMAP(n) (0x0270 + ((n) * 4)) argument
220 #define BLENDERQ_Q_FUNC_F(n) (n << 18) argument
221 #define BLENDERQ_P_FUNC_F(n) (n << 12) argument
222 #define BLENDERQ_B_FUNC_F(n) (n << 6) argument
[all …]
/drivers/phy/rockchip/
A Dphy-rockchip-typec.c147 #define XCVR_PSM_RCTRL(n) ((0x4001 | ((n) << 9)) << 2) argument
175 #define TX_PSC_A0(n) ((0x4100 | ((n) << 9)) << 2) argument
176 #define TX_PSC_A1(n) ((0x4101 | ((n) << 9)) << 2) argument
177 #define TX_PSC_A2(n) ((0x4102 | ((n) << 9)) << 2) argument
178 #define TX_PSC_A3(n) ((0x4103 | ((n) << 9)) << 2) argument
246 #define RX_PSC_A0(n) ((0x8000 | ((n) << 9)) << 2) argument
247 #define RX_PSC_A1(n) ((0x8001 | ((n) << 9)) << 2) argument
248 #define RX_PSC_A2(n) ((0x8002 | ((n) << 9)) << 2) argument
249 #define RX_PSC_A3(n) ((0x8003 | ((n) << 9)) << 2) argument
250 #define RX_PSC_CAL(n) ((0x8006 | ((n) << 9)) << 2) argument
[all …]
/drivers/gpu/drm/sun4i/
A Dsun6i_mipi_dsi.c59 #define SUN6I_DSI_BASIC_SIZE0_VSA(n) ((n) & 0xfff) argument
63 #define SUN6I_DSI_BASIC_SIZE1_VACT(n) ((n) & 0xfff) argument
70 #define SUN6I_DSI_INST_FUNC_LANE_DEN(n) ((n) & 0xf) argument
76 #define SUN6I_DSI_INST_LOOP_NUM_N0(n) ((n) & 0xfff) argument
91 #define SUN6I_DSI_TCON_DRQ_SET(n) ((n) & 0x3ff) argument
95 #define SUN6I_DSI_PIXEL_CTL0_FORMAT(n) ((n) & 0xf) argument
102 #define SUN6I_DSI_PIXEL_PH_VC(n) (((n) & 3) << 6) argument
103 #define SUN6I_DSI_PIXEL_PH_DT(n) ((n) & 0x3f) argument
123 #define SUN6I_DSI_BLK_PF(n) (((n) & 0xffff) << 16) argument
124 #define SUN6I_DSI_BLK_PD(n) ((n) & 0xff) argument
[all …]
/drivers/mailbox/
A Dsun6i-msgbox.c23 #define CTRL_RX(n) BIT(0 + 8 * ((n) % 4)) argument
24 #define CTRL_TX(n) BIT(4 + 8 * ((n) % 4)) argument
31 #define RX_IRQ(n) BIT(0 + 2 * (n)) argument
33 #define TX_IRQ(n) BIT(1 + 2 * (n)) argument
36 #define FIFO_STAT_REG(n) (0x0100 + 0x4 * (n)) argument
70 int n; in sun6i_msgbox_irq() local
102 int n = channel_number(chan); in sun6i_msgbox_send_data() local
118 int n = channel_number(chan); in sun6i_msgbox_startup() local
142 int n = channel_number(chan); in sun6i_msgbox_shutdown() local
165 int n = channel_number(chan); in sun6i_msgbox_last_tx_done() local
[all …]
/drivers/gpu/drm/mxsfb/
A Dlcdif_regs.h150 #define DISP_SIZE_DELTA_Y(n) (((n) & 0xffff) << 16) argument
152 #define DISP_SIZE_DELTA_X(n) ((n) & 0xffff) argument
155 #define HSYN_PARA_BP_H(n) (((n) & 0xffff) << 16) argument
157 #define HSYN_PARA_FP_H(n) ((n) & 0xffff) argument
160 #define VSYN_PARA_BP_V(n) (((n) & 0xffff) << 16) argument
162 #define VSYN_PARA_FP_V(n) ((n) & 0xffff) argument
167 #define VSYN_HSYN_WIDTH_PW_H(n) ((n) & 0xffff) argument
190 #define CTRLDESCL0_1_WIDTH(n) ((n) & 0xffff) argument
197 #define CTRLDESCL0_3_PITCH(n) ((n) & 0xffff) argument
200 #define CTRLDESCL_HIGH0_4_ADDR_HIGH(n) ((n) & 0xf) argument
[all …]
/drivers/usb/dwc3/
A Dcore.h253 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) argument
263 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) argument
270 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) argument
294 #define DWC3_GSTS_CURMOD(n) ((n) & 0x3) argument
305 #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) argument
319 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) argument
321 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) argument
460 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) argument
593 #define DWC3_DALEPENA_EP(n) BIT(n) argument
919 #define DWC3_MODE(n) ((n) & 0x7) argument
[all …]
/drivers/crypto/inside-secure/
A Dsafexcel.h40 #define EIP206_OPT_ICE_TYPE(n) ((n>>8)&3) argument
41 #define EIP206_OPT_OCE_TYPE(n) ((n>>10)&3) argument
230 #define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n) argument
236 #define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n) argument
246 #define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24) argument
280 #define EIP197_CDR_IRQ(n) BIT((n) * 2) argument
281 #define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1) argument
305 #define EIP197_G_IRQ_DFE(n) BIT((n) << 1) argument
308 #define EIP197_G_IRQ_PE(n) BIT((n) + 20) argument
357 #define EIP197_CONTEXT_SIZE(n) (n) argument
[all …]
/drivers/vhost/
A Dtest.c43 static void handle_vq(struct vhost_test *n) in handle_vq()
100 struct vhost_test *n = container_of(vq->dev, struct vhost_test, dev); in handle_vq_kick() local
107 struct vhost_test *n = kmalloc(sizeof *n, GFP_KERNEL); in vhost_test_open() local
130 static void *vhost_test_stop_vq(struct vhost_test *n, in vhost_test_stop_vq()
142 static void vhost_test_stop(struct vhost_test *n, void **privatep) in vhost_test_stop()
147 static void vhost_test_flush(struct vhost_test *n) in vhost_test_flush()
154 struct vhost_test *n = f->private_data; in vhost_test_release() local
166 static long vhost_test_run(struct vhost_test *n, int test) in vhost_test_run()
217 static long vhost_test_reset_owner(struct vhost_test *n) in vhost_test_reset_owner()
241 static int vhost_test_set_features(struct vhost_test *n, u64 features) in vhost_test_set_features()
[all …]
/drivers/net/ethernet/meta/fbnic/
A Dfbnic_csr.h240 #define FBNIC_INTR_CQ_REARM(n) \ argument
250 #define FBNIC_INTR_RCQ_TIMEOUT(n) \ argument
253 #define FBNIC_INTR_TCQ_TIMEOUT(n) \ argument
444 #define FBNIC_TCE_RAM_TCAM(m, n) \ argument
601 #define FBNIC_RXB_DROP_BYTES_STS_L(n) \ argument
747 #define FBNIC_RPC_TCAM_ACT(m, n) \ argument
753 #define FBNIC_RPC_TCAM_MACDA(m, n) \ argument
765 #define FBNIC_RPC_TCAM_IPSRC(m, n)\ argument
767 #define FBNIC_RPC_TCAM_IPDST(m, n)\ argument
770 #define FBNIC_RPC_RSS_TBL(n, m) \ argument
[all …]
/drivers/gpu/drm/bridge/
A Dchipone-icn6211.c30 #define PD_CTRL(n) (0x0a + ((n) & 0x3)) /* 0..3 */ argument
31 #define RST_CTRL(n) (0x0e + ((n) & 0x1)) /* 0..1 */ argument
32 #define SYS_CTRL(n) (0x10 + ((n) & 0x7)) /* 0..4 */ argument
38 #define RGB_DRV(n) (0x18 + ((n) & 0x3)) /* 0..3 */ argument
39 #define RGB_DLY(n) (0x1c + ((n) & 0x1)) /* 0..1 */ argument
50 #define HFP_HSW_HBP_HI_HS(n) (((n) & 0x300) >> 6) argument
56 #define BIST_POL_BIST_MODE(n) (((n) & 0xf) << 4) argument
86 #define PLL_REF_DIV_P(n) ((n) & 0xf) argument
88 #define PLL_REF_DIV_S(n) (((n) & 0x7) << 5) argument
108 #define DSI_CTRL_DSI_LANES(n) ((n) & 0x3) argument
[all …]
/drivers/gpu/drm/renesas/rcar-du/
A Drcar_du_regs.h72 #define DSSR_DFB(n) (1 << ((n)+15)) argument
78 #define DSSR_ADC(n) (1 << ((n)-1)) argument
86 #define DSRCR_ADCL(n) (1 << ((n)-1)) argument
95 #define DIER_ADCE(n) (1 << ((n)-1)) argument
104 #define DPPR_DPE(n) (1 << ((n)*4-1)) argument
106 #define DPPR_DPS_SHIFT(n) (((n)-1)*4) argument
289 #define DPLLCR_N(n) ((n) << 5) argument
290 #define DPLLCR_M(n) ((n) << 3) argument
298 #define DPLLC2R_M(n) ((n) << 8) argument
299 #define DPLLC2R_FDPLL(n) ((n) << 0) argument
[all …]
/drivers/net/ethernet/ti/icssg/
A Dicssg_classifier.c30 #define FT1_N_REG(slize, n, reg) \ argument
48 #define FT1_CFG_SHIFT(n) (2 * (n)) argument
65 #define FT3_N_REG(slize, n, reg) \ argument
74 #define RX_CLASS_N_REG(slice, n, reg) \ argument
80 #define RX_CLASS_GATES_N_REG(slice, n) \ argument
113 #define FT1_CFG_SHIFT(n) (2 * (n)) argument
216 int n, const u8 *addr) in rx_class_ft1_set_da()
228 int n, const u8 *addr) in rx_class_ft1_set_da_mask()
327 int n; in icssg_class_disable() local
372 int n; in icssg_class_default() local
[all …]

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