| /drivers/phy/ |
| A D | phy-core-mipi-dphy.c | 20 static int phy_mipi_dphy_calc_config(unsigned long pixel_clock, in phy_mipi_dphy_calc_config()
81 int phy_mipi_dphy_get_default_config(unsigned long pixel_clock, in phy_mipi_dphy_get_default_config()
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_snps_hdmi_pll.c | 131 static void compute_hdmi_tmds_pll(u64 pixel_clock, u32 refclk, in compute_hdmi_tmds_pll()
219 void intel_snps_hdmi_pll_compute_mpllb(struct intel_mpllb_state *pll_state, u64 pixel_clock) in intel_snps_hdmi_pll_compute_mpllb()
291 void intel_snps_hdmi_pll_compute_c10pll(struct intel_c10pll_state *pll_state, u64 pixel_clock) in intel_snps_hdmi_pll_compute_c10pll()
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| A D | intel_vdsc.c | 1056 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); in intel_vdsc_min_cdclk() local
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| /drivers/video/fbdev/ |
| A D | atafb.c | 822 static struct pixel_clock { struct
823 unsigned long f; /* f/[Hz] */
824 unsigned long t; /* t/[ps] (=1/f) */
825 int right, hsync, left; /* standard timing in clock cycles, not pixel */
827 int sync_mask; /* or-mask for hw.falcon.sync to set this clock */
828 int control_mask; /* ditto, for hw.falcon.vid_control */
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| /drivers/gpu/drm/amd/display/include/ |
| A D | bios_parser_types.h | 119 uint32_t pixel_clock; /* khz */ member
132 uint32_t pixel_clock; /* in KHz */ member
161 uint32_t pixel_clock; member
204 uint32_t pixel_clock; member
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| /drivers/staging/sm750fb/ |
| A D | ddk750_mode.h | 28 unsigned long pixel_clock; member
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| /drivers/gpu/drm/amd/display/dc/bios/ |
| A D | command_table.c | 1654 uint32_t pixel_clock, in dac_encoder_control_prepare_params()
1672 uint32_t pixel_clock, in dac1_encoder_control_v1()
1693 uint32_t pixel_clock, in dac2_encoder_control_v1()
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| /drivers/gpu/drm/amd/display/dc/virtual/ |
| A D | virtual_link_encoder.c | 46 uint32_t pixel_clock) {} in virtual_link_encoder_enable_tmds_output()
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_encoders.c | 206 u32 pixel_clock) in amdgpu_dig_monitor_is_duallink()
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| /drivers/media/i2c/ |
| A D | ov5645.c | 81 u32 pixel_clock; member
99 struct v4l2_ctrl *pixel_clock; member
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| A D | ov7251.c | 81 u32 pixel_clock; member
145 struct v4l2_ctrl *pixel_clock; member
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| /drivers/media/i2c/et8ek8/ |
| A D | et8ek8_reg.h | 39 u32 pixel_clock; /* in Hz */ member
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| /drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_link_encoder.c | 923 uint32_t pixel_clock) in dcn10_link_encoder_enable_tmds_output()
960 uint32_t pixel_clock) in dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa()
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| /drivers/gpu/drm/radeon/ |
| A D | radeon_encoders.c | 368 u32 pixel_clock) in radeon_dig_monitor_is_duallink()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_link_encoder.c | 1051 uint32_t pixel_clock) in dce110_link_encoder_enable_tmds_output()
1087 uint32_t pixel_clock) in dce110_link_encoder_enable_lvds_output()
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| /drivers/gpu/drm/gma500/ |
| A D | oaktrail.h | 13 u16 pixel_clock; member
46 u16 pixel_clock; member
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| /drivers/gpu/drm/vc4/ |
| A D | vc4_dpi.c | 94 struct clk *pixel_clock; member
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| A D | vc4_hdmi.h | 156 struct clk *pixel_clock; member
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| /drivers/media/platform/rockchip/rkisp1/ |
| A D | rkisp1-csi.c | 156 s64 pixel_clock; in rkisp1_csi_start() local
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| /drivers/gpu/drm/amd/pm/swsmu/inc/ |
| A D | smu_v14_0.h | 64 uint32_t pixel_clock; member
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| A D | smu_v13_0.h | 69 uint32_t pixel_clock; member
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| A D | smu_v11_0.h | 77 uint32_t pixel_clock; member
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| /drivers/media/platform/qcom/camss/ |
| A D | camss-vfe.c | 925 u64 pixel_clock[VFE_LINE_NUM_MAX]; in vfe_set_clock_rates() local
1006 u64 pixel_clock[VFE_LINE_NUM_MAX]; in vfe_check_clock_rates() local
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| /drivers/gpu/drm/exynos/ |
| A D | exynos_hdmi.c | 81 int pixel_clock; member
919 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) in hdmi_find_phy_conf()
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| /drivers/gpu/drm/ |
| A D | drm_displayid_internal.h | 116 u8 pixel_clock[3]; member
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