| /drivers/rtc/ |
| A D | rtc-aspeed.c | 25 u32 reg1, reg2; in aspeed_rtc_read_time() local
55 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
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| /drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
| A D | irq_service_dcn21.c | 186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
200 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
| A D | irq_service_dcn31.c | 181 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
195 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
| A D | irq_service_dcn314.c | 183 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
197 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
| A D | irq_service_dcn30.c | 193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
207 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
| A D | irq_service_dcn302.c | 178 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
| A D | irq_service_dcn315.c | 188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
202 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /drivers/gpu/drm/amd/display/dc/irq/dcn401/ |
| A D | irq_service_dcn401.c | 172 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
186 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
| A D | irq_service_dcn32.c | 192 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
206 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /drivers/gpu/drm/amd/display/dc/irq/dcn351/ |
| A D | irq_service_dcn351.c | 159 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
173 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
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| /drivers/gpu/drm/amd/display/dc/irq/dcn35/ |
| A D | irq_service_dcn35.c | 180 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
194 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
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| /drivers/gpu/drm/amd/display/dc/irq/dcn36/ |
| A D | irq_service_dcn36.c | 158 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
172 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_pmdemand.c | 404 u32 reg1, reg2; in intel_pmdemand_init_pmdemand_params() local
519 u32 *reg1, u32 *reg2, bool serialized) in intel_pmdemand_update_params()
579 u32 reg2, mod_reg2; in intel_pmdemand_program_params() local
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| /drivers/net/ethernet/sunplus/ |
| A D | spl2sw_mdio.c | 20 u32 reg, reg2; in spl2sw_mdio_access() local
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| /drivers/net/ethernet/netronome/nfp/bpf/ |
| A D | verifier.c | 50 const struct bpf_reg_state *reg2) in nfp_record_adjust_head()
175 const struct bpf_reg_state *reg2 = cur_regs(env) + BPF_REG_2; in nfp_bpf_check_helper_call() local
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| /drivers/media/dvb-frontends/ |
| A D | tua6100.c | 65 u8 reg2[] = { 0x02, 0x00, 0x00 }; in tua6100_set_params() local
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| A D | s5h1409.c | 556 u16 reg, reg1, reg2; in s5h1409_set_qam_interleave_mode() local
594 u16 reg, reg1, reg2; in s5h1409_set_qam_interleave_mode_legacy() local
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| /drivers/gpu/drm/amd/display/dc/irq/dce120/ |
| A D | irq_service_dce120.c | 76 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /drivers/mcb/ |
| A D | mcb-parse.c | 43 __le32 reg2; in chameleon_parse_gdd() local
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| /drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
| A D | irq_service_dcn10.c | 173 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
| A D | irq_service_dcn20.c | 176 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
| A D | irq_service_dcn303.c | 121 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /drivers/clk/ |
| A D | clk-axi-clkgen.c | 329 unsigned int reg1, unsigned int reg2, in axi_clkgen_set_div()
417 unsigned int reg1, unsigned int reg2) in axi_clkgen_get_div()
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| /drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
| A D | irq_service_dcn201.c | 125 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /drivers/net/ethernet/mellanox/mlxbf_gige/ |
| A D | mlxbf_gige_mdio.c | 139 u32 reg1, reg2; in calculate_i1clk() local
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